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14-bit ccd signal processor with v-driver and precision timing tm generator ad9927 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features integrated 18-channel v-driver 1.8 v afetg core internal ldo regulator and charge pump circuitry compatibility with 3 v or 1.8 v systems 24 programmable vertical clock signals correlated double sampler (cds) with ?3 db, 0 db, +3 db, and +6 db gain 6 db to 42 db, 10-bit variable gain amplifier (vga) 14-bit, 40 mhz analog-to-digital converter (adc) black level clamp with variable level control complete on-chip timing generator precision timing core with ~400 ps resolution on-chip 3 v horizontal and rg drivers general-purpose outputs (gpos) for shutter and system support on-chip driver for external crystal on-chip sync generator with external sync input 128-lead csp_bga package, 9 mm 9 mm, 0.65 mm pitch applications digital still cameras general description the ad9927 is a highly integrated ccd signal processor for digital still camera applications. it includes a complete analog front end with a/d conversion, combined with a full-function programmable timing generator and 18-channel vertical driver (v-driver). the timing generator is capable of supporting up to 24 vertical clock signals to control advanced ccds. the on- chip v-driver supports up to 18 channels for use with 5-field ccds. a precision timing core allows adjustment of high speed clocks with approximately 400 ps resolution at 40 mhz operation. the ad9927 also contains eight general-purpose outputs, which can be used for shutter and system functions. the analog front end includes black level clamping, cds, vga, and a 14-bit adc. the timing generator provides all the necessary ccd clocks: rg, h-clocks, v-clocks, sensor gate pulses, substrate clock, and substrate bias control. the ad9927 is specified over an operating temperature range of C25c to +85c. functional block diagram ad9927 cds vga clamp 14-bit adc sl sck sdata cli vref 6db to 42db horizontal drivers vertical timing control rg h1 to h8 24 reft refb precision timing generator sync generator internal clocks hd vd sync internal registers ccdin ?3db,0db,+3db,+6db 14 hl clo gp01 to gp08 xv1 to xv24 xsubck 3v output 1.8v input 8 8 charge pump 1.8v output 3v input ldo reg vertical driver 18 subck xsubcnt rstb v 1a-v6 (3-level) v7-v15 (2-level) dout 05892-103 figure 1.
ad9927 rev. 0 | page 2 of 100 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 specifications..................................................................................... 3 digital specifications ................................................................... 4 analog specifications................................................................... 5 timing specifications .................................................................. 6 vertical driver specifications ..................................................... 7 absolute maximum ratings............................................................ 8 package thermal characteristics ............................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 terminology .................................................................................... 12 typical performance characteristics ........................................... 13 equivalent circuits ......................................................................... 14 system overview ............................................................................ 15 high speed precision timing core........................................... 16 horizontal clamping and blanking......................................... 20 horizontal timing sequence example.................................... 26 vertical timing generation ...................................................... 28 vertical sequences (vseq) ....................................................... 31 internal vertical driver connections...................................... 45 vertical timing example........................................................... 53 shutter timing control ............................................................. 55 substrate clock operation (subck) ...................................... 55 field counters............................................................................. 58 general-purpose outputs (gpo s ) .......................................... 59 gp look-up tables (lut)........................................................ 63 complete exposure/readout operation using primary counter and gpo signals .............................. 64 manual shutter operation using enhanced sync modes .... 66 analog front-end description and operation...................... 70 power-up sequence for master mode..................................... 72 standby mode operation .......................................................... 76 cli frequency change.............................................................. 76 circuit layout information........................................................... 78 serial interface timing .............................................................. 82 layout of internal registers ...................................................... 83 updating new register values ................................................. 84 complete register listing ............................................................. 85 outline dimensions ....................................................................... 99 ordering guide .......................................................................... 99 revision history 1/06revision 0: initial version
ad9927 rev. 0 | page 3 of 100 specifications table 1. parameter min typ max unit temperature range operating ?25 +85 c storage ?65 +150 c power supply voltage inputs avdd (afe analog supply) 1.6 1.8 2.0 v tcvdd (timing core supply) 1.6 1.8 2.0 v clivdd (cli input supply) 1.6 3.0 3.6 v rgvdd (rg, hl driver) 2.7 3.0 3.6 v hvdd (h1 to h8 drivers) 2.7 3.0 3.6 v dvdd (digital logic) 1.6 1.8 2.0 v drvdd (parallel data output drivers) 1.6 3.0 3.6 v iovdd (digital i/o) 2.7 3.0 3.6 v xvvdd (vertical output drivers) 2.7 3.0 3.6 v cp1p8 (cp supply input) 1.6 1.8 2.0 v ldoin (ldo supply input) 2.25 3.0 3.6 v v-driver power supply voltages vdd1, vdd2 (v-driver logic) 2.7 3.0 3.6 v vh1, vh2 (v-driver high supply) 11.5 15.0 16.5 v vl1, vl2 (v-driver low supply) ?8.5 ?7.5 ?5.5 v vm1, vm2 (v-driver mid supply) ?1.5 0.0 +1.5 v vll (subck low supply) ?8.5 ?7.5 ?5.5 v vmm (subck mid supply) ?4.0 0.0 +0.3 v power supply currents40 mhz operation avdd (1.8 v) 27 ma tcvdd (1.8 v) 5 ma clivdd (3 v) 1.5 ma rgvdd (3.3 v, 20 pf rg load, 20 pf hl load) 10 ma hvdd 1 (3.3 v, 480 pf total load on h1 to h8) 59 ma dvdd (1.8 v) 9.5 ma drvdd (3 v, 10 pf load on each dout pin) 6 ma iovdd (3 v, depends on load and output frequency of digital i/o) 2 ma xvvdd (3 v, depends on load and output frequency of xv signals) 2 ma power supply currentsstandby mode operation standby1 mode 12 ma standby2 mode 5 ma standby3 mode 1.5 ma maximum clock rate (cli) 40 mhz 1 the total power dissipated by the hvdd (or rgvdd) supply can be approximated using the equation total hvdd power = [ c l hvdd pixel frequency ] hvdd reducing the capacitive load and/or reducing the hvdd supply reduces the power dissipation. c l is the total capacitance seen by all h-outputs.
ad9927 rev. 0 | page 4 of 100 digital specifications iovdd = 1.6 v to 3.6 v, rgvdd = hvdd = 2.7 v to 3.6 v, c l = 20 pf, t min to t max , unless otherwise noted. table 2. parameter symbol min typ max unit logic inputs (iovdd) high level input voltage v ih v dd ? 0.6 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs (iovdd, xvdd, drvdd) high level output voltage @ i oh = 2 ma v oh v dd ? 0.5 v low level output voltage @ i ol = 2 ma v ol 0.5 v rg and h-driver outputs (hvdd, rgvdd) high level output voltage @ maximum current v oh v dd ? 0.5 v low level output voltage @ maximum current v ol 0.5 v maximum output current (programmable) 18 ma maximum load capacitance (for each output) 60 pf
ad9927 rev. 0 | page 5 of 100 analog specifications avdd = 1.8 v, f cli = 40 mhz, typical timing specifications, t min to t max , unless otherwise noted. table 3. parameter min typ max unit notes cds 1 allowable ccd reset transient 0.5 1.2 v cds gain accuracy vga gain = 6.3 db (code 15, default value) ?3.0 db cds gain ?3.3 ?2.8 ?2.3 db 0 db cds gain ?0.5 0 +0.5 db +3 db cds gain 2.4 2.9 3.4 db +6 db cds gain 5.0 5.5 6.0 db maximum input range before saturation vga gain = 6.3 db (code 15, default value) ?3 db cds gain 1.4 v p-p 0 db cds gain 1.0 v p-p +3 db cds gain 0.7 v p-p +6 db cds gain 0.5 v p-p allowable ob pixel amplitude 1 0 db cds gain (default) ?100 +200 mv +6 db cds gain ?50 +100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range low gain (vga code 15, default) 6.3 db maximum gain (vga code 1023) 42.4 db black level clamp clamp level resolution 1024 steps clamp level measured at adc output minimum clamp level (code 0) 0 lsb maximum clamp level (code 1023) 255 lsb adc resolution 14 bits differential nonlinearity (dnl) ?1.0 0.5 lsb no missing codes guaranteed integral nonlinearity (inl) 4 16 lsb full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 1.4 v reference bottom voltage (refb) 0.4 v system performance includes entire signal chain gain accuracy 0 db cds gain low gain (vga code 15) 5.8 6.3 6.8 db gain = (0.0358 code) + 5.76 db maximum gain (vga code 1023) 41.9 42.4 42.9 db peak nonlinearity, 1.0 v input signal 0.1 0.3 % 6 db vga gain, 0 db cds gain applied total output noise 0.5 lsb rms ac-gro unded input, 6 db vga gain applied power supply rejection (psr) 50 db measured with step change on supply 1 input signal characteristics defined as follows: 200mv max optical black pixel 500mv typ reset transient 1v max input signal range (0db cds gain) 05892-002
ad9927 rev. 0 | page 6 of 100 timing specifications c l = 20 pf, avdd = dvdd = tcvdd = 1.8 v, drvdd = 3.0 v, f cli = 40 mhz, unless otherwise noted. table 4. parameter symbol min typ max unit master clock (see figure 16) cli clock period t conv 25 ns cli high/low pulse width 10 12.5 15 ns delay from cli rising edge to internal pixel position 0 t clidly 6 ns vd falling edge to hd falling edge in slave mode (see figure 89) t vdhd 0 vd period ? 5 t conv ns afe clpob pulse width (see figure 23 and figure 33) 1, 2 2 20 pixels afe sample location (see figure 17 and figure 20) 1 shp sample edge to shd sample edge t s1 11 12.5 ns data outputs (see figure 21 and figure 22) output delay from dclk rising edge t od 1 ns inhibited area for doutphase edge location t doutinh shdloc + 1 shdloc + 15 edge location pipeline delay from shp/shd sampling to dout 16 cycles serial interface (see figure 97) maximum sck frequency (must not exceed cli frequency) f sclk 40 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns 1 parameter is programmable. 2 minimum clpob pulse width is for functional operation only. wide r typical pulses are recommended to achieve good clamp perform ance.
ad9927 rev. 0 | page 7 of 100 vertical driver specifications vh1, vh2 = 15 v. vm1, vm2, vmm = 0 v. vl1, vl2, vll = ?7.5 v. c l shown in load model, 25c. table 5. parameter symbol min typ max unit v-driver outputs (simplified load conditions, 3000 pf to ground) delay time, vl to vm and vm to vh t plm , t pmh 35 ns delay time, vm to vl and vh to vm t pml , t phm 35 ns rise time, vl to vm t rlm 125 ns rise time, vm to vh t rmh 260 ns fall time, vm to vl t fml 220 ns fall time, vh to vm t fhm 125 ns output currents @ ?7.25 v 10 ma @ ?0.25 v ?22 ma @ +0.25 v 22 ma @ +14.75 v ?10 ma r on 35 subck output (simplified load conditions, 1000 pf to ground) delay time, vll to vh t plh 25 ns delay time, vh to vll t phl 30 ns delay time, vll to vmm t plm 25 ns delay time, vmm to vh t pmh 25 ns delay time, vh to vmm t phm 30 ns delay time, vmm to vll t pml 25 ns rise time, vll to vh t rlh 40 ns rise time, vll to vmm t rlm 45 ns rise time, vmm to vh t rmh 30 ns fall time, vh to vll t fhl 40 ns fall time, vh to vmm t fhm 90 ns fall time, vmm to vll t fml 25 ns output currents @ ?7.25 v 20 ma @ ?0.25 v ?12 ma @ +0.25 v 12 ma @ +14.75 v ?20 ma r on 35 v-driver input t rlm , t rmh , t rlh 50% 10% 90% t plm , t pmh , t plh v-driver output 10% 50% 90% t fml , t fhm , t fhl t pml , t phm , t phl 05892-114 figure 2. definition of v-driver timing specifications
ad9927 rev. 0 | page 8 of 100 absolute maximum ratings table 6. parameter with respect to rating avdd avss ?0.3 v to +2.0 v tcvdd tcvss ?0.3 v to +2.0 v hvdd1, hvdd2 hvss1, hvss2 ?0.3 v to +3.9 v rgvdd rgvss ?0.3 v to +3.9 v dvdd dvss ?0.3 v to +2.0 v drvdd drvss ?0.3 v to +3.9 v iovdd iovss ?0.3 v to +3.9 v xvvdd dvss ?0.3 v to +3.9 v clivdd tcvss ?0.3 v to +3.9 v ldoin ldovss ?0.3 v to +3.9 v cp1p8 cpvss ?0.3 v to +2.0 v vh1, vh2 vl1 ?0.3 v to +25.0 v vh1, vh2 vss1 ?0.3 v to +17.0 v vl1, vl2 vss1 ?17.0 v to +0.3 v vm1, vm2 vss1 ?6.0 v to +0.3 v vll vss1 ?17.0 v to +0.3 v vmm vss1 ?6.0 v to +0.3 v v5v vss1 ?0.3 v to +6.0 v v1a to v15 vss1 vl ? 0.3 v to vh + 0.3 v rg output rgvss ?0.3 v to rgvdd + 0.3 v h1 to h8, hl output hvss ?0.3 v to hvdd + 0.3 v digital outputs dvss ?0.3 v to iovdd + 0.3 v digital inputs dvss ?0.3 v to iovdd + 0.3 v sck, sl, sdata dvss ?0.3 v to iovdd + 0.3 v reft, refb, ccdin avss ?0.3 v to avdd + 0.3 v junction temperature 150c lead temperature, 10 sec 350c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics thermal resistance csp_bga package: ja = 40.3c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9927 rev. 0 | page 9 of 100 pin configuration and fu nction descriptions bottom view (not to scale) 121110987654321 a b c d e f g h j k l m 05892-115 figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description l7 avdd p afe supply: 1.8 v l8 avss p analog supply ground b11 dvdd p digital logic supply: 1.8 v c10 dvss p digital logic ground a2 drvdd p data driver supply: 1.8 v, 3.3 v a1 drvss p data driver ground m6 tcvss p analog ground for timing core l6 tcvdd p timing core supply: 1.8 v l5 clivdd p cli input supply: 3.3 v k12 iovdd p digital i/o supply: 1.8 v, 3.3 v (gpio, subck, hd/vd, sl, sck, sdata, sync, rstb) j12 iovss p digital i/o ground h12 xvvdd p xv output supply: 1.8 v, 3.3 v c4 vl1 p v-driver low supply m2 vl2 p v-driver low supply c5 vh1 p v-driver high supply l3 vh2 p v-driver high supply c3 vm1 p v-driver mid supply k3 vm2 p v-driver mid supply g10 vss1 p v-driver ground d11 vss2 p v-driver ground k5 vll p v-driver low supply for subck output j5 vmm p v-driver mid supply for subck output h9 vdd1 p v-driver logic supply (3 v) c11 vdd2 p v-driver logic supply (3 v) d1 cp1p8 p charge pump 1.8 v input c2 cpvss p charge pump ground b1 cp3p3 p charge pump 3.3 v output e2 ldoin p ldo 3.3 v input e11 ldovss p ldo ground h1 hvdd1 p h-driver supply 1: 3.3 v g2 hvss1 p h-driver ground 1 l1 hvdd2 p h-driver supply 2: 3.3 v k2 hvss2 p h-driver ground 2 m4 rgvdd p rg driver supply: 3.3 v l4 rgvss p rg driver ground e10 v5v p connect to 3 v supply through diode
ad9927 rev. 0 | page 10 of 100 pin no. mnemonic type 1 description m7 ccdin ai ccd signal input e1 sense ai ldo output sense pin f1 ldoout ao ldo output voltage b2 cpfct ao charge pump flying capacitor top c1 cpfcb ao charge pump flying capacitor bottom m8 reft ao voltage reference top bypass m9 refb ao voltage reference bottom bypass k7 cli di reference clock input l9 sl di 3-wire serial load pulse. internal pull-up resistor. m10 sdata di 3-wire serial data input m11 sck di 3-wire serial clock d2 cpcli di charge pump clock input f9 ldo3p2en di ldo 3.2 v output enable f10 ldo1p8en di ldo 1.8 v output enable g11 sync di external system sync input f11 rstb di external reset input (active low pulse to reset). internal pull-up resistor. h10 xsubcnt di generates 3-level output for subck. connect high if 3-level subck not used. h11 vd dio vertical sync pulse (input for slave mode, output for master mode) j11 hd dio horizontal sync pulse (input for slave mode, output for master mode) m12 gpo8 dio general-purpose output 8 l10 gpo7 dio general-purpose output 7 l11 gpo6 dio general-purpose output 6 k9 gpo5 dio general-purpose output 5 l12 gpo4 dio general-purpose output 4 k10 gpo3 dio general-purpose output 3 k11 gpo2 dio general-purpose output 2 j10 gpo1 dio general-purpose output 1 k6 clo do clock output for crystal f2 h1 do ccd horizontal clock 1 g1 h2 do ccd horizontal clock 2 h2 h3 do ccd horizontal clock 3 j1 h4 do ccd horizontal clock 4 j2 h5 do ccd horizontal clock 5 k1 h6 do ccd horizontal clock 6 l2 h7 do ccd horizontal clock 7 m1 h8 do ccd horizontal clock 8 m3 hl do ccd last horizontal clock m5 rg do ccd reset gate clock a10 d0 do data output 0 (lsb). b9 d1 do data output 1. a9 d2 do data output 2. b8 d3 do data output 3. a8 d4 do data output 4. b7 d5 do data output 5. a7 d6 do data output 6. b6 d7 do data output 7. a6 d8 do data output 8. b5 d9 do data output 9. a5 d10 do data output 10. b4 d11 do data output 11. a4 d12 do data output 12. b3 d13 do data output 13 (msb).
ad9927 rev. 0 | page 11 of 100 pin no. mnemonic type 1 description a3 dclk do data clock output. k4 subck vo3 ccd substrate clock j3 v1a vo3 ccd vertical transfer clock. 3-level output (xv1 + xv16) j4 v1b vo3 ccd vertical transfer clock. 3-level output (xv1 + xv17) h3 v2a vo3 ccd vertical transfer clock. 3-level output (xv2 + xv18) h4 v2b vo3 ccd vertical transfer clock. 3-level output (xv2 + xv19) g4 v3a vo3 ccd vertical transfer clock. 3-level output (xv3 + xv20) g3 v3b vo3 ccd vertical transfer clock. 3-level output (xv3 + xv21) f3 v4 vo3 ccd vertical transfer clock. 3-level output (xv4 + xv22) f4 v5 vo3 ccd vertical transfer clock. 3-level output (xv5 + xv23) e4 v6 vo3 ccd vertical transfer clock. 3-level output (xv6 + xv24) e3 v7 vo2 ccd vertical transfer clock. 2-level output (xv7) d4 v8 vo2 ccd vertical transfer clock. 2-level output (xv8) d3 v9 vo2 ccd vertical transfer clock. 2-level output (xv9) d5 v10 vo2 ccd vertical transfer clock. 2-level output (xv10) d6 v11 vo2 ccd vertical transfer clock. 2-level output (xv11) d7 v12 vo2 ccd vertical transfer clock. 2-level output (xv12) c7 v13 vo2 ccd vertical transfer clock. 2-level output (xv13) c8 v14 vo2 ccd vertical transfer clock. 2-level output (xv14) d8 v15 vo2 ccd vertical transfer clock. 2-level output (xv15) j8 test0 ao do not connect j7 test1 ao do not connect k8 test2 di connect to 1.8 v/3 v supply d10 test3 di connect to ground j6 test4 ai connect to ground g9 test5 ai connect to ground j9 test6 di connect to ground a11, a12, b10, b12, c6, c9, c12, d9, d12, e9, e12, f12, g12 nc not internally connected 1 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power, vo2 = v ertical driver output 2-level, vo3 = vertical driver output 3-level.
ad9927 rev. 0 | page 12 of 100 terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. therefore, every code must have a finite width. no missing codes guaranteed to 14-bit resolution indicates that all 16,384 codes, each for its respective input, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ad9927 from a true straight line. the point used as zero scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level 1 lsb and 0.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is always appropriately gained up to fill the adcs full-scale range. tot a l o utput noi s e the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage using the relationship 1 lsb = ( adc full scale /2 n codes ) where n is the bit resolution of the adc. for the ad9927, 1 lsb is 0.122 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage.
ad9927 rev. 0 | page 13 of 100 typical performance characteristics frequency (mhz) 40 15 20 25 30 35 power (mw) 500 400 450 350 300 250 200 100 150 50 0 2.7v/1.8v 3.0v/1.8v 3.3v/1.8v 0 5892-004 figure 4. afetg power vs. frequency (v-driver not included) (avdd = tcvdd = dvdd = 1.8 v, all other supplies at 2.7 v, 3.0 v, or 3.3 v) 0 adc output code 0 dnl (lsb) 1.0 ?1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 2k 4k 6k 8k 10k 12k 14k 16k 0 5892-116 figure 5. typical differential nonlinearity (dnl) performance cds + vga gain (db) 45 0 rms output noise (lsb) 150 0 100 50 5 10152025303540 +3db cds 0db cds ?3db cds 0 5892-006 figure 6. output noise vs. total gain (cds + vga) adc output code 0 inl (lsb) 2 ?7 2k 4k 6k 8k 10k 12k 14k 16k 1 0 ?1 ?2 ?3 ?4 ?5 ?6 05892-117 figure 7. typical system nonlinearity performance
ad9927 rev. 0 | page 14 of 100 equivalent circuits r a v dd avss avss 05892-008 figure 8. ccdin d v dd dvss drvss dr v dd three- state data dout 05892-009 figure 9. digital data outputs io v dd iovss 330 ? 05892-010 figure 10. digital inputs h v dd o r rgvdd hvss or rgvss three-state rg, h1 to h8 output 05892-011 figure 11. h1 to h8, hl, rg drivers internal reference voltage v5v v h 05892-119 figure 12. v5v
ad9927 rev. 0 | page 15 of 100 system overview figure 13 shows the typical system block diagram for the ad9927 in master mode. the ccd output is processed by the ad9927s afe circuitry, which consists of a cds, vga, black level clamp, and adc. the digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. to operate the ccd, all ccd timing parameters are programmed into the ad9927 from the system microprocessor through the 3-wire serial interface. from the master clock, cli, provided by the image processor or external crystal, the ad9927 generates the ccds horizontal and vertical clocks and internal afe clocks. external synchronization is provided by a sync pulse from the microprocessor, which resets the internal counters and resyncs the vd and hd outputs. ccdin gpo1 to gpo8 h1 to h8, hl, rg, vsub v 1a to v 15, subck ccd ad9927 afetg v-driver digital image processing asic dout dclk hd, vd cli serial interface sync p 05892-120 figure 13. typical system block diagram, master mode alternatively, the ad9927 can be operated in slave mode. in this mode, the vd and hd are provided externally from the image processor, and all ad9927 timing is synchronized with vd and hd. the h-drivers for h1 to h8, hl, and rg are included in the ad9927, allowing these clocks to be directly connected to the ccd. an h-driver voltage of up to 3.3 v is supported. v1a to v15 and subck vertical clocks are included as well, allowing the ad9927 to provide all horizontal and vertical clocks necessary to clock data out of a ccd. the ad9927 includes programmable general-purpose outputs (gpo), which can trigger mechanical shutter and strobe (flash) circuitry. figure 14 and figure 15 show the maximum horizontal and vertical counter dimensions for the ad9927. all internal horizontal and vertical clocking is controlled by these counters, which specify line and pixel locations. maximum hd length is 8192 pixels per line, and maximum vd length is 8192 lines per field. 13-bit horizontal = 8192 pixels max 13-bit vertical = 8192 lines max m a x imum counter dimensions 05892-013 figure 14. vertical and horizontal counters vd hd max vd length is 8192 lines cli max hd length is 8192 pixels 05892-014 figure 15. maximum vd/hd dimensions
ad9927 rev. 0 | page 16 of 100 high speed precision timing core the ad9927 generates high speed timing signals using the flexible precision timing core. this core is the foundation for generating the timing used for both the ccd and the afe; it includes the reset gate rg, horizontal drivers h1 to h8, hl, and shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. the high speed timing of the ad9927 operates the same way in either master or slave mode configuration. for more information on synchronization and pipeline delays, see the power-up sequence for master mode section. timing resolution the precision timing core uses a 1 master clock input as a reference (cli). this clock should be the same as the ccd pixel clock frequency. figure 16 illustrates how the internal timing core divides the master clock period into 64 steps or edge positions. using a 40 mhz cli frequency, the edge resolution of the precision timing core is approximately 0.4 ns. if a 1 system clock is not available, it is possible to use a 2 reference clock by programming the clidivide register (afe register address 0x0d). the ad9927 then internally divides the cli frequency by 2. the ad9927 includes a master clock output, clo, which is the inverse of cli. this output should be used as a crystal driver. a crystal can be placed between the cli and clo pins to generate the master clock for the ad9927. high speed clock programmability figure 17 shows when the high speed clocks rg, h1 to h8, shp, and shd are generated. the rg pulse has programmable rising and falling edges and can be inverted using the polarity control. horizontal clock h1 has programmable rising and falling edges and polarity control. in hclk mode 1, h3, h5, and h7 are equal to h1 and h2, h4, h6, and h8 are always inverses of h1. the edge location registers are each six bits wide, allowing the selection of all 64 edge locations. figure 20 shows the default timing locations for all of the high speed clock signals. p[0] p[64] = p[0] p[16] p[32] p[48] o ne pixel period cli t clidly position notes 1. the pixel clock period is divided into 64 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period position (t clidly ). 05892-015 figure 16. high speed clock resoluti on from cli, master clock input hl ccd signal rg programmable clock positions: 1 shp sample location. 2 shd sample location. 3 rg rising edge. 4 rg falling edge. 5 h1 rising edge. 6 h1 falling edge. 7 hl rising edge. 8 hl falling edge. 1 2 34 78 h2, h4, h6, h8 h1, h3, h5, h7 56 05892-016 figure 17. high speed clock programmable locations (hclkmode = 001)
ad9927 rev. 0 | page 17 of 100 h-driver and rg outputs in addition to the programmable timing positions, the ad9927 features on-chip output drivers for the rg, hl, and h1 to h8 outputs. these drivers are powerful enough to drive the ccd inputs directly. the h-driver and rg current can be adjusted for optimum rise/fall time for a particular load by using the drive strength control registers (addresses 0x35 and 0x36). the 3-bit drive setting for each output is adjustable in 4.3 ma increments: 0 = three-state; 1 = 4.3 ma; 2 = 8.6 ma; 3 = 12.9 ma; and 4, 5, 6, 7 = 17.2 ma. as shown in figure 17, when hclk mode 1 is used, the h2, h4, h6, and h8 outputs are inverses of the h1, h3, h5, and h7 outputs, respectively. using the hclkmode register (address 0x23, bits [9:7]), it is possible to select a different configuration. table 9 shows a comparison of the different programmable settings for each hclk mode. figure 18 and figure 19 show the settings for hclk mode 2 and hclk mode 3, respectively. note that it is recommended that all h1 to h8 outputs on the ad9927 be used together for maximum flexibility in drive strength settings. a typical ccd with h1 and h2 inputs should only have the ad9927s h1, h3, h5, and h7 outputs connected together to drive the ccds h1, and the h2, h4, h6, and h8 outputs connected together to drive the ccds h2. similarly, a ccd with h1, h2, h3, and h4 inputs should have ? h1 and h3 connected to the ccds h1. ? h2 and h4 connected to the ccds h2. ? h5 and h7 connected to the ccds h3. ? h6 and h8 connected to the ccds h4. table 8. timing core register para meters for h1, h2, hl, rg, shp, shd parameter length range description polarity 1b high/low polarity control for h1, h2, hl, and rg (0 = inversion, 1 = no inversion) positive edge 6b 0 to 63 edge location positive edge location for h1, h2, hl, and rg negative edge 6b 0 to 63 edge location ne gative edge location for h1, h2, hl, and rg sampling location 6b 0 to 63 edge location sa mpling location for internal shp and shd signals drive strength 3b 0 to 4 current steps drive current for h1 to h8 , hl, and rg outputs (4.3 ma per step) table 9. hclk modes, selected by address 0x23, bits [9:7] hclkmode register value description mode 1 001 h1 edges are programmable, with h3 = h5 = h7 = h1, h2 = h4 = h6 = h8 = inverse of h1 mode 2 010 h1 edges are programmable, with h3 = h5 = h7 = h1 h2 edges are programmable, with h4 = h6 = h8 = h2 mode 3 100 h1 edges are programmable, with h3 = h1 and h2 = h4 = inverse of h1 h5 edges are programmable, with h7 = h5 and h6 = h8 = inverse of h5 invalid selection 000, 011, 101, 110, 111 invalid register settings 12 43 h1 to h8 programmable locations: 1 h1 rising edge. 2 h1 falling edge. 3 h2 rising edge. 4 h2 falling edge. h2, h4, h6, h8 h1, h3, h5, h7 05892-017 figure 18. hclk mode 2 operation
ad9927 rev. 0 | page 18 of 100 h1 to h8 programmable edges: 1 h1 rising edge. 2 h1 falling edge. 3 h5 rising edge. 4 h5 falling edge. h1, h3 h2, h4 h5, h7 h6, h8 12 34 0 5892-018 figure 19. hclk mode 3 operation p[0] pixel period rg hl p[64] = p[0] ccd signal p[32] p[16] p[48] notes 1. all signal edges are fully programmable to any of the 64 positions within one pixel period. default positions for each signal are shown. hclk mode 1 is shown. 2. connect h1, h3, h5, and h7 together and h2, h4, h6, and h8 together for maximum drive strength. position h2, h4, h6, h8 rgr[0] rgf[16] hlr[0] hlf[32] h1, h3, h5, h7 h1r[0] h1f[32] shp[32] t s1 shd[0] 0 5892-019 figure 20. high speed timing default locations digital data outputs the ad9927 data output and dclk phase are programmable using the doutphase registers (address 0x38, bits [11:0]). doutphasep (bits [5:0]) selects any edge location from 0 to 63, as shown in figure 21. doutphasen (bits [11:6]) does not actually program the phase of the data outputs but is used internally and should always be programmed to a value of doutphasep plus 32 edges. for example, if doutphasep is set to 0, doutphasen should be set to 32 (0x20). normally, the dout and dclk signals track in phase, based on the contents of the doutphase registers. the dclk output phase can also be held fixed with respect to the data outputs by changing the dclkmode register high (address 0x38, bit [12]). in this mode, the dclk output remains at a fixed phase equal to a delayed version of cli while the data output phase is still programmable. the pipeline delay through the ad9927 is shown in figure 22. after the ccd input is sampled by shd, there is a 16-cycle delay until the data is available.
ad9927 rev. 0 | page 19 of 100 p[0] p[64] = p[0] pixel period p[16] p[32] p[48] dout dclk t od notes 1. data output (dout) and dclk phase are adjustable with respect to the pixel period. 2. within one clock period, the data transition can be programmed to 64 different locations. 3. dclk can be inverted with respect to dout by using the dclkinv register. 0 5892-020 figure 21. digital output phase adjustment using doutphasep register notes 1. timing values shown are shdloc = 0, with dclkmode = 0. 2. higher values of shd and/or dout phase shifts dout t ransition to the right, with r espect to cli location. 3. recommended value for dout phase is to use shploc or up to 15 edges following shploc. dclk dout ccdin cli shd (internal) adc dout (internal) nn+2 n+1 n+3 n+13 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+14 sample pixel n n+16 n+17 n+15 n?14 n?4 n?5 n?6 n?7 n?8 n?9 n?10 n?11 n?12 n?13 n?3 n?2 n?1 n n+1 n?15 n?16 n?17 t clidly pipeline latency = 16 cycles n?14 n?4 n?5 n?6 n?7 n?8 n?9 n?10 n?11 n?12 n?13 n?3 n?2 n?1 n n+1 n?15 n?16 n?17 t doutinh 05892-021 figure 22. digital data output pipeline delay
ad9927 rev. 0 | page 20 of 100 horizontal clamping and blanking the ad9927s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. individual control is provided for clpob, pblk, and hblk in the different regions of each field. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts. individual clpob and pblk patterns the afe horizontal timing consists of clpob and pblk, as shown in figure 23. these two signals are programmed independently using the registers in table 10. the start polarity for the clpob (and pblk) signal is clpobpol (pblkpol), and the first and second toggle positions of the pulse are clpobtog1 (pblktog1) and clpobtog2 (pblktog2). both signals are active low and should be programmed accordingly. a separate pattern for clpob and pblk can be programmed for each vertical sequence. as described in the ver t ical timing generation section, several v-sequences can be created, each containing a unique pulse pattern for clpob and pblk. figure 49 shows how the sequence change positions divide the readout field into different regions. by assigning a different v-sequence to each region, the clpob and pblk signals can change with each change in the vertical timing. clpob and pblk masking areas additionally, the ad9927 allows the clpob and pblk signals to be disabled in certain lines in the field without changing any of the existing clpob pattern settings. to use clpob (or pblk) masking, the clpmaskstart (pblkmaskstart) and clpmaskend (pblkmaskend) registers are programmed to specify the start and end lines in the field where the clpob (pblk) patterns are ignored. the three sets of start and end registers allow up to three clpob (pblk) masking areas to be created. the clpob and pblk masking registers are not specific to a certain v-sequence; they are always active for any existing field of timing. during operation, to disable the clpob masking feature, these registers must be set to the maximum value of 0x1fff or a value greater than the programmed vd length. note that to disable clpob (and pblk) masking during power-up, it is recommended to set clpmaskstart (pblkmaskstart) to 8191 and clpmaskend (p blkmaskend) to 0. this prevents any accidental masking caused by register update events. table 10. clpob and pblk pattern registers register length range description clpobpol 1b high/low starting polarity of clpob for each v-sequence. pblkpol 1b high/low starting polar ity of pblk for each v-sequence. clpobtog1 13b 0 to 8191 pixel location first clpo b toggle position within line for each v-sequence. clpobtog2 13b 0 to 8191 pixel location second clpo b toggle position within line for each v-sequence. pblktog1 13b 0 to 8191 pixel location first pblk toggle position within line for each v-sequence. pblkbtog2 13b 0 to 8191 pixel location second pblk toggle position within line for each v-sequence. clpmaskstart 13b 0 to 8191 line location clpob masking ar eastarting line within field (maximum of three areas). clpmaskend 13b 0 to 8191 line location clpob masking ar eaending line within field (maximum of three areas). pblkmaskstart 13b 0 to 8191 line location pblk masking areastarting line wi thin field (maximum of three areas). pblkmaskend 13b 0 to 8191 line location pblk masking ar eaending line within field (maximum of three areas).
ad9927 rev. 0 | page 21 of 100 3 2 1 hd clpob pblk programmable settings: 1 start polarity (clamp and blank region are active low). 2 first toggle position. 3 second toggle position. active active 05892-022 figure 23. clamp and preblank pulse placement no clpob signal for line 600 vd hd no clpob signal for lines 6 to 8 clpmaskstart1 = 6 clpmaskend1 = 8 0 1 2 597 598 clpmaskstart2 = clpmaskend2 = 600 clpob 05892-023 figure 24. clpob masking example
ad9927 rev. 0 | page 22 of 100 individual hblk patterns the hblk programmable timing shown in figure 25 is similar to clpob and pblk; however, there is no start polarity control. only the toggle positions are used to designate the start and stop positions of the blanking period. additionally, there are separate masking polarity controls for h1, h2, and hl that designate the polarity of the horizontal clock signals during the blanking period. setting hblkmask_h1 high sets h1, and therefore h3, h5, and h7, low during the blanking, as shown in figure 26. as with the clpob and pblk signals, hblk registers are available in each v-sequence, allowing different blanking signals to be used with different vertical timing sequences. the ad9927 supports three modes of hblk operation. hblk mode 0 supports basic operation and some support for special hblk patterns. hblk mode 1 supports pixel mixing hblk operation. hblk mode 2 supports advanced hblk operation. the following sections describe each mode in detail. register parameters are described in detail in table 11. hblk mode 0 operation there are six toggle positions available for hblk. normally, only two of the toggle positions are used to generate the standard hblk interval. however, the additional toggle positions can be used to generate special hblk patterns, as shown in figure 27. the pattern in this example uses all six toggle positions to generate two extra groups of pulses during the hblk interval. by changing the toggle positions, different patterns can be created. separate toggle positions are available for even and odd lines. if alternation is not needed, the same values should be loaded into the registers for even (hblktoge) and odd (hblktogo) lines. hd hblk basic hblk pulse is generated using hblktoge1 and hblktoge2 registers (hblkalt = 0) blank blank hblktoge1 hblktoge2 05892-024 figure 25. typical horizontal blanking pulse placement (hblkmode = 0) hd hblk h1/h3/h5/h7 h1/h3/h5/h7 h2/h4/h6/h8 the polarity of h1/h3/h5/h7 during blanking is programmable (h2/h4/h6/h8 and hl are separately programmable) 0 5892-025 figure 26. hblk masking polarity control hblk special h-blank pattern is created using multiple hblk toggle positions (hblkalt = 0) h1/h3 h2/h4 hblktoge1 hblktoge2 hblktoge3 hblktoge4 hblktoge5 hblktoge6 05892-026 figure 27. using multiple toggle positions for hblk (hblkmode = 0)
ad9927 rev. 0 | page 23 of 100 table 11. hblk pattern registers register length range description hblkmode 2b 0 to 2 hblk modes enable s different hblk toggle position operation. 0: normal mode. six toggle positions available for even and odd lines. if even/odd alternation is not needed , set toggles for even/odd the same. 1: pixel mixing mode. in addition to the six toggle positions, the hblkstart, hblkend, hblklen, and hblkrep register s can be used to generate hblk patterns. if even/odd alternation is not need, set toggles for even/odd the same. 2: advanced hblk mode. divides hblk in terval into six repeat areas. uses hblkstarta/b/c and ra*h*repa/b/c registers. 3: test mode only. do not access. hblkstart 13b 0 to 8191 pixel location start locati on for hblk in hblk mode 1 and hblk mode 2. hblkend 13b 0 to 8191 pixel location end location for hblk in hblk mode 1 and hblk mode 2. hblklen 13b 0 to 8191 pixels hblk length in hblk mode 1 and hblk mode 2. hblkrep 13b 0 to 8191 repetitions number of hblk repetitions in hblk mode 1 and hblk mode 2. hblkmask_h1 1b high/low masking polar ity for h1, h3, h5, h7 during hblk. hblkmask_h2 1b high/low masking polar ity for h2, h4, h6, h8 during hblk. hblkmask_hl 1b high/low masking polarity for hl during hblk. hblktogo1 13b 0 to 8191 pixel location first hblk toggle position for odd lines in hblk mode 0 and hblk mode 1. hblktogo2 13b 0 to 8191 pixel location second hblk toggle pos ition for odd lines in hblk mode 0 and hblk mode 1. hblktogo3 13b 0 to 8191 pixel location third hblk toggle pos ition for odd lines in hblk mode 0 and hblk mode 1. hblktogo4 13b 0 to 8191 pixel location fourth hblk toggle position for odd line s in hblk mode 0 and hblk mode 1. hblktogo5 13b 0 to 8191 pixel location fifth hblk toggle pos ition for odd lines in hblk mode 0 and hblk mode 1. hblktogo6 13b 0 to 8191 pixel location sixth hblk toggle pos ition for odd lines in hblk mode 0 and hblk mode 1. hblktoge1 13b 0 to 8191 pixel location fi rst hblk toggle position for even lines in hblk mode 0 and hblk mode 1. hblktoge2 13b 0 to 8191 pixel location second hblk toggle pos ition for even lines in hblk mode 0 and hblk mode 1. hblktoge3 13b 0 to 8191 pixel location third hblk toggle pos ition for even lines in hblk mode 0 and hblk mode 1. hblktoge4 13b 0 to 8191 pixel location fourth hblk toggle pos ition for even lines in hblk mode 0 and hblk mode 1. hblktoge5 13b 0 to 8191 pixel location fifth hblk toggle posit ion for even lines in hblk mode 0 and hblk mode 1. hblktoge6 13b 0 to 8191 pixel location sixth hblk toggle posit ion for even lines in hblk mode 0 and hblk mode 1. ra0h1repa/b/c 12b 0 to 15 hclk pulses for each a, b, and c hblk repeat area 0. number of h1 repetitions for hblkstarta/b/c in hblk mode 2 for even lines; o dd lines defined using hblkalt_pat. [3:0] ra0h1repa. number of h1 pulses following hblkstarta. [7:4] ra0h1repb. number of h1 pulses following hblkstartb. [11:8] ra0h1repc. number of h1 pulses following hblkstartc. ra1h1repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 1. number of h1 repetitions for hblkstarta/b/c. ra2h1repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 2. number of h1 repetitions for hblkstarta/b/c. ra3h1repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 3. number of h1 repetitions for hblkstarta/b/c. ra4h1repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 4. number of h1 repetitions for hblkstarta/b/c. ra5h1repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 5. number of h1 repetitions for hblkstarta/b/c. ra0h2repa/b/c 12b 0 to 15 hclk pulses for each a, b, and c hblk repeat area 0. number of h2 repetitions for hblkstarta/b/c in hblk mode 2 for even lines; o dd lines defined using hblkalt_pat. [3:0] ra0h2repa. number of h2 pulses following hblkstarta. [7:4] ra0h2repb. number of h2 pulses following hblkstartb. [11:8] ra0h2repc. number of h2 pulses following hblkstartc. ra1h2repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 1. number of h2 repetitions for hblkstarta/b/c. ra2h2repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 2. number of h2 repetitions for hblkstarta/b/c. ra3h2repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 3. number of h2 repetitions for hblkstarta/b/c. ra4h2repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 4. number of h2 repetitions for hblkstarta/b/c. ra5h2repa/b/c 12b 0 to 15 hclk pulses hblk repeat area 5. number of h2 repetitions for hblkstarta/b/c. hblkstarta 13b 0 to 8191 pixel location hblk repeat area st art position a for hblk mode 2. set to 8191 if not used. hblkstartb 13b 0 to 8191 pixel location hb lk repeat area start position b for hblk mode 2. set to 8191 if not used. hblkstartc 13b 0 to 8191 pixel location hblk repeat area st art position c for hblk mode 2. set to 8191 if not used.
ad9927 rev. 0 | page 24 of 100 register length range description hblkalt_pat1 3b 0 to 5 even repeat area hblk mode 2, odd field repeat area 0 pattern, selected from even field repeat areas previously defined. hblkalt_pat2 3b 0 to 5 even repeat area hb lk mode 2, odd field repeat area 1 pattern. hblkalt_pat3 3b 0 to 5 even repeat area hb lk mode 2, odd field repeat area 2 pattern. hblkalt_pat4 3b 0 to 5 even repeat area hb lk mode 2, odd field repeat area 3 pattern. hblkalt_pat5 3b 0 to 5 even repeat area hb lk mode 2, odd field repeat area 4 pattern. hblkalt_pat6 3b 0 to 5 even repeat area hb lk mode 2, odd field repeat area 5 pattern. hblk h-blank repeating pattern is created using hblklen and hblkrep registers h1/h3 h2/h4 hblkstart hblktoge1 hblktoge2 hblkend hblktoge3 hblktoge4 hblklen hblkrep number 1 hblkrep number 2 hblkrep number 3 hblkrep = 3 05892-027 figure 28. hblk repeating pattern using hblkmode = 1 hblk mode 1 operation multiple repeats of the hblk signal are enabled by setting hblkmode to 1. in this mode, the hblk pattern can be generated using a different set of registers: hblkstart, hblkend, hblklen, and hblkrep, along with the six toggle positions (see figure 28). separate toggle positions are available for even and odd lines. if alternation is not needed, the same values should be loaded into the registers for even (hblktoge) and odd (hblktogo) lines. generating hblk line alternation hblk mode 0 and hblk mode 1 provide the ability to alternate different hblk toggle positions on even and odd lines. hblk line alternation can be used in conjunction with v-pattern odd/even alternation or on its own. separate toggle positions are available for even and odd lines. if even/odd line alternation is not required, the same values should be loaded into the registers for even (hblktoge) and odd (hblktogo) lines. increasing h-clock width during hblk hblk mode 0 and hblk mode 1 allow the h1 to h8 pulse width to be increased during the hblk interval. as shown in figure 29, the h-clock frequency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. to enable this feature, the hclk_width register (address 0x34, bits [7:4]) is set to a value between 1 and 15. when this register is set to 0, the wide hclk feature is disabled. the reduced frequency occurs only for h1 to h8 pulses that are located within the hblk area. the hclk_width register is generally used in conjunction with special hblk patterns to generate vertical and horizontal mixing in the ccd. note that the wide hclk feature is available only in hblk mode 0 and hblk mode 1. hblk mode 2 does not support wide hclks. table 12. hclk width register register length description hclk_width 4b controls h1 to h8 width during hblk as a fraction of pixel rate 0: same frequency as pixel rate 1: 1/2 pixel frequency, that is, doubles the hclk pulse width 2: 1/4 pixel frequency 3: 1/6 pixel frequency 4: 1/8 pixel frequency 5: 1/10 pixel frequency 15: 1/30 pixel frequency
ad9927 rev. 0 | page 25 of 100 hblk h-clock frequency can be reduced during hblk by 1/2 (as shown), 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 using hblkwidth register h1/h3 h2/h4 1/f pix 2(1/f pix ) 05892-028 figure 29. generating wide h-clock pulses during hblk interval h1 h2 hblkstart a hblkend repeat area 0 hd b c repeat area 1 repeat area 2 repeat area 3 repeat area 4 repeat area 5 mask a, b, c pulses in any repeat area by setting ra*h*rep* = 0 change number of a, b, c pulses in any repeat area using ra*h*rep* registers create up to 3 groups of toggles a, b, c common in all repeat areas 0 5892-029 figure 30. hblk mode 2 operation hblk h1 h2 hblkstart hblkstarta hblkend hblklen repeat area 0 hblkrep = 2 to create two repeat areas hd repeat area 1 hblkstartb hblkstartc ra0h1re pa ra0h1repb ra0h1repc all ra*h*repa/b/c registers = 2 to create two hclk pulses ra1h1repa ra1h1repb ra1h1repc ra0h2repa ra0h2repb ra0h2repc ra1h2re pa ra1h2repb ra1h2repc 0 5892-030 figure 31. hblk mode 2 registers
ad9927 rev. 0 | page 26 of 100 hblk mode 2 operation hblk mode 2 allows more advanced hblk pattern operation. if multiple areas of hclk pulses that are unevenly spaced apart from one another are needed, hblk mode 2 can be used. using a separate set of registers, hblk mode 2 can divide the hblk region into up to six repeat areas (see table 11). as shown in figure 31, each repeat area shares a common group of toggle positions, hblkstarta, hblkstartb, and hblkstartc. however, the number of toggles following each start position can be unique in each repeat area by using the rah1rep and rah2rep registers. as shown in figure 30, setting the rah1repa/rah1repb/rah1repc or rah2repa/ rah2repb/rah2repc registers to 0 masks hclk groups from appearing in a particular repeat area. figure 31 shows only two repeat areas being used, although six are available. it is possible to program a separate number of repeat area repetitions for h1 and h2, but generally the same value is used for both h1 and h2. figure 31 shows an example of ra0h1repa/ra0h1repb/ ra0h1repc = ra0h2repa/ra0h2repb/ra0h2repc = ra1h1repa/ra1h1repb/ra1h1repc = ra1h2repa/ ra1h2repb/ra1h2repc = 2. furthermore, hblk mode 2 allows a different hblk pattern on even and odd lines. the hblkstarta, hblkstartb, and hblkstartc registers, as well as the rah1repa/rah1repb/ rah1repc and rah2repa/rah2repb/rah2repc registers, define operation for the even lines. for separate control of the odd lines, the hblkalt_pat registers specify up to six repeat areas on the odd lines by reordering the repeat areas used for the even lines. new patterns are not available, but the order of the previously defined repeat areas on the even lines can be changed for the odd lines to accommodate advanced ccd operation. horizontal timing sequence example figure 32 shows an example ccd layout. the horizontal register contains 28 dummy pixels, which occur on each line clocked from the ccd. in the vertical direction, there are 10 optical black (ob) lines at the front of the readout and two at the back of the readout. the horizontal direction has four ob pixels in the front and 48 in the back. figure 33 shows the basic sequence layout to be used during the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob signals. pblk is optional and is often used to blank the digital outputs during the hblk time. hblk is used during the vertical shift interval. because pblk is used to isolate the cds input (see the analog preblanking section), the pblk signal should not be used during clpob operation. the change in the offset behavior that occurs during pblk impacts the accuracy of the clpob circuitry. the hblk, clpob, and pblk parameters are programmed in the v-sequence registers. more elaborate clamping schemes, such as adding in a separate sequence to clamp in the entire shield ob lines, can be used. this requires configuring a separate v-sequence for clocking out the ob lines. the clpmask registers are also useful for disabling the clpob on a few lines without affecting the setup of the clamping sequences. it is important that clpob be used only during valid ob pixels. during other portions on the frame timing, such as vertical blanking or sg line timing, the ccd does not output valid ob pixels. any clpob pulse that occurs during this time causes errors in clamping operation and changes in the black level of the image. horizontal ccd register effective image area 28 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines v h 0 5892-031 figure 32. example ccd configuration
ad9927 rev. 0 | page 27 of 100 vertical shift vert. shift ccd output shp shd h1/h3/h5/h7 h2/h4/h6/h8 hblk pblk clpob optical black dummy effective pixels optic a lbl a ck optical black hd notes 1. pblk active (low) should not be used during clpob active (low). 0 5892-032 figure 33. horizontal sequence example
ad9927 rev. 0 | page 28 of 100 vertical timing generation the ad9927 provides a flexible solution for generating vertical ccd timing and can support multiple ccds and different system architectures. the vertical transfer clocks are used to shift each line of pixels into the horizontal output register of the ccd. the ad9927 allows these outputs to be individually programmed into various readout configurations by using a 4-step process. figure 34 shows an overview of how the vertical timing is generated in four steps. 1. the individual pulse patterns for xv1 to xv24 are created by using the vertical pattern group registers. 2. the v-pattern groups are used to build the sequences, which is where additional information is added. 3. the readout for an entire field is constructed by dividing the field into different regions and then assigning a sequence to each region. each field can contai n up to nine different regions to accommodate different steps of the readout, such as high speed line shifts and unique vertical line transfers. the total number of v-patterns, v-sequences, and fields is programmable, but limited by the number of registers. 4. the mode registers allow the different fields to be combined in any order for various readout configurations.
ad9927 rev. 0 | page 29 of 100 region 0: use v-sequence 3 region 1: use v-sequence 2 region 2: use v-sequence 1 region 0: use v-sequence 3 region 1: use v-sequence 2 region 2: use v-sequence 1 region 0: use v-sequence 2 region 1: use v-sequence 0 region 3: use v-sequence 0 region 4: use v-sequence 2 xv1 xv2 xv23 xv24 xv1 xv2 xv3 field 0 field1 field2 region 2: use v-sequence 3 field0 field1 field2 field3 field4 field5 field1 field4 field2 xv3 xv23 xv24 vpat0 xv1 xv2 xv23 xv24 xv3 xv1 xv2 xv23 xv24 xv3 xv1 xv2 xv23 xv24 xv3 vpat1 1 2 3 4 create the vertical pattern groups, up to four toggle positions for each output. build the v-sequences by adding start polarity, line start position, number of repeats, alternation, group a/b/c/d information, and hblk/clpob pulses. v-sequence 0 (vpat0, 1 rep) v-sequence 1 (vpat1, 2 rep) v-sequence 2 (vpat1, n rep) build each field by dividing into different regions and assigning a different v-sequence to each (maximum of nine regions in each field). use the mode registers to control which fields are used, and in what order (maximum of seven fields may be combined in any order). 05892-033 figure 34. summary of vertical timing generation
ad9927 rev. 0 | page 30 of 100 vertical pattern groups (vpat) the vertical pattern groups define the individual pulse patterns for each xv1 to xv24 output signal. table 13 summarizes the registers available for generating each of the v-pattern groups. the first, second, third, and fourth toggle positions (vtog1, vtog2, vtog3, and vtog4) are the pixel locations within the line where the pulse transitions. all toggle positions are 13-bit values, allowing their placement anywhere in the horizontal line. more registers are included in the vertical sequence registers to specify the output pulses. vpol specifies the start polarity for each signal; vstart specifies the start position of the v-pattern group within the line; vlen designates the total length of the v-pattern group, which determines the number of pixels between each of the pattern repetitions when repetitions are used. the vstart position is actually an offset value for each toggle position. the actual pixel location for each toggle, measured from the hd falling edge (pixel 0), is equal to the vstart value plus the toggle position. when the selected v-output is designated as a vsg pulse, either the vtog1/vtog2 or vtog3/vtog4 pair is selected using v-sequence address 0x02, vsgpatsel. all four toggle positions are not simultaneously available for vsg pulses. all unused v-channels must have their toggle positions programmed to either 0 or maximum value. this prevents unpredictable behavior because the default values of the v-pattern group registers are unknown. table 13. vertical pattern group registers register length description vtog1 13b first toggle position within line for ea ch xv1 to xv24 output, relative to vstart value vtog2 13b second toggle position, relative to vstart value vtog3 13b third toggle position, relative to vstart value vtog4 13b fourth toggle position, relative to vstart value hd xv1 4 1 2 3 xv2 1 2 3 xv24 1 23 start position of v ertical p a ttern group is programm a ble in v ertic a l sequence registers. programmable settings: 1 start polarity (located in v-sequence registers). 2 first toggle position. 3 second toggle position (third and fourth toggle positions also available for more complex patterns). 4 total pattern length for all vertical outputs (located in vertical sequence registers). 05892-034 figure 35. vertical pattern group programmability
ad9927 rev. 0 | page 31 of 100 vertical sequences (vseq) the vertical sequences are created by selecting one of the v-pattern groups and adding repeats, start position, horizontal clamping, and blanking information. the v-sequences are programmed using the registers shown in table 14. figure 36 shows how the different registers are used to generate each v-sequence. the vpatsela, vpatselb, vpatselc, and vpatseld registers select which v-pattern is used in a given v-sequence. having four groups available allows different vertical outputs to be mapped to different v-patterns. the selected v-pattern group can have repetitions added for high speed line shifts or for line binning by using the vrep registers for odd and even lines. generally, the same number of repetitions is programmed into both registers. if a different number of repetitions is required on odd and even lines, separate values can be used for each register (see the generating line alternation for v- sequences and hblk section). the vstarta and vstartb registers specify where in the line the v-pattern group starts. the vmask_en register is used in conjunction with the freeze/resume registers to enable optional masking of the v-outputs. either or both of the freeze1/resume1 and freeze2/resume2 registers can be enabled. the line length (in pixels) is programmable using the hdlen registers. each v-sequence can have a different line length to accommodate various image readout techniques. the maximum number of pixels per line is 8192. the last line of the field is programmed separately using the hdlastlen register, which is located in the field register section. vrep 3 hd xv1 to xv24 v-pattern group 1 3 clpob hblk 2 44 vrep 2 5 6 programmable settings for each vertical sequence: 1 start position in the line of selected v-pattern group. 2 hd line length. 3 v-pattern select (vpatsel) to select any v-pattern group. 4 number of repetitions of the v-pattern group (if needed). 5 start polarity and toggle positions for clpob and pblk signals. 6 masking polarity and toggle positions for hblk signal. 05892-035 figure 36. v-sequence programmability
ad9927 rev. 0 | page 32 of 100 table 14. summary of v-sequence registers (see table 10 and table 11 for the hblk, clpob, and pblk register summary) register length description hold 4b use in conjunction with vmask_en. 1 = hold function instead of freeze/resume function. vmask_en 4b enables the masking of v1 to v24 outputs at the lo cations specified by the freeze/resume registers. 1= enable masking for all groups. one bit for each set of freeze and resume positions 1 to 4. concat_grp 4b combines toggle positions of groups a/b/c/d when enabled. only group a settings for start, polarity, length, and repetition are used when this mode is selected. 0 = disable. 1 = enable the addition of all toggle positions from vpatsela/b/c/d. 2 = test mode only. do not use. 15 = test mode only. do not use. vrep_mode 2b selects line alternatio n for v-output repetitions. note separate control for group a and groups b/c/d. 0 = disable alternation. group a uses vrepa_1, groups b/c/d use vrep _even for all lines. 1 = 2-line. group a alternates vrepa_1 and vrepa _2. groups b/c/d alternate vrep_even and vrep_odd. 2 = 3-line. group a alternates vrepa_1, vrepa_2, and vrepa_3. groups b/c/d follow a vrep_even, vrep_odd, vrep_odd, vrep_even, vrep_odd, vrep_odd pattern. 3 = 4-line. group a alternates vrepa_1, vrepa_2, vrep a_3, vrepa_4. groups b/c/d follow 2-line alternation. lastreplen_en 4b enables a separate pattern length to be used during the last repetition of the v-sequence. one bit for each group (a, b, c, and d). set bit high to enable . group a is the lsb. recommended value is enabled. lasttog_en 4b enables a final toggle position to be added at the en d of the v-sequence. the toggle position is shared by all v-outputs in the same group. one bit for each group. set bit high to enable. group a is the lsb. hdlene 13b hd line length for even lines in the v-sequence. hdlen0 13b hd line length for odd lines in the v-sequence. vpol_a 24b group a start polarity bits for each xv1 to xv24 signal. vpol_b 24b group b start polarity bits for each xv1 to xv24 signal. vpol_c 24b group c start polarity bits for each xv1 to xv24 signal. vpol_d 24b group d start polarity bits for each xv1 to xv24 signal. groupsel_0 24b assigns each xv1 to xv12 signal to either group a/b/c/ d. two bits for each signal. bits [1:0] are for xv1, bits [3:2] are for xv2 bits [23:22] are for xv12. 0 = assign to group a, 1 = group b, 2 = group c, and 3 = group d. groupsel_1 24b assigns each xv13 to xv24 signal to either group a/b/c/d. two bits for each signal. bits [1:0] are for xv13, bits [3:2] are for xv14 bits [23:22] are for xv24. 0 = assign to group a, 1 = group b, 2 = group c, and 3 = group d. vpatsela 5b selected v-pattern for group a. vpatselb 5b selected v-pattern for group b. vpatselc 5b selected v-pattern for group c. vpatseld 5b selected v-pattern for group d. vstarta 13b start position for the selected v-pattern group a. vstartb 13b start position for the selected v-pattern group b. vstartc 13b start position for the selected v-pattern group c. vstartd 13b start position for the selected v-pattern group d. vlena 13b length of selected v-pattern group a. vlenb 13b length of selected v-pattern group b. vlenc 13b length of selected v-pattern group c. vlend 13b length of selected v-pattern group d. vrepa_1 13b number of repetitions for the v-pattern group a for first lines (even). vrepa_2 13b number of repetitions for the v-pattern group a for second lines (odd). vrepa_3 13b number of repetitions for the v-pattern group a for third lines. vrepa_4 13b number of repetitions for the v-pattern group a for fourth lines. vrepb_odd 13b number of repetitions for the v-pattern group b for odd lines. vrepc_odd 13b number of repetitions for the v-pattern group c for odd lines.
ad9927 rev. 0 | page 33 of 100 register length description vrepd_odd 13b number of repetitions for the v-pattern group d for odd lines. vrepb_even 13b number of repetitions for the v-pattern group b for even lines. vrepc_even 13b number of repetitions for the v-pattern group c for even lines. vrepd_even 13b number of repetitions for the v-pattern group d for even lines. freeze1 13b pixel location where the v-outputs freeze or hold (s ee vmask_en). also used as valtsel0_even [12:0] register when special vseqalt_en mode is enabled. freeze2 13b pixel location where the v-outputs freeze or hold (s ee vmask_en). also used as valtsel1_even [12:0] register when special vseqalt_en mode is enabled. freeze3 13b pixel location where the v-outputs freeze or hold (see vmask_en). also used as valtsel0_odd [12:0] register when special vseqalt_en mode is enabled. freeze4 13b pixel location where the v-outputs freeze or hold (see vmask_en). also used as valtsel1_odd [12:0] register when special vseqalt_en mode is enabled. resume1 13b pixel location where the v-outputs resume operation (see vmask_en). also used as valtsel0_even [17:13] register when special vseqalt_en mode is enabled. resume 2 13b pixel location where the v-outputs resume operation (see vmask_en). also used as valtsel1_even [17:13] register when special vseqalt_en mode is enabled. resume3 13b pixel location where the v-outputs resume operation (see vmask_en). also used as valtsel0_odd [17:13] register when special vseqalt_en mode is enabled. resume4 13b pixel location where the v-outputs resume operation (see vmask_en). also used as valtsel1_odd [17:13] register when special vseqalt_en mode is enabled. lastreplen_a 13b separate length for last repetition of vertic al pulses. must be enabled using lastreplen_en. should be programmed to a value equal to the vlena register. lastreplen_b 13b separate length for last repetition of vertic al pulses. must be enabled using lastreplen_en. should be programmed to a value equal to the vlenb register. lastreplen_c 13b separate length for last repetition of vertic al pulses. must be enabled using lastreplen_en. should be programmed to a value equal to the vlenc register. lastreplen_d 13b separate length for last repetition of vertic al pulses. must be enabled using lastreplen_en. should be programmed to a value equal to the vlend register. lasttog_a 13b optional fifth toggle position for the vertical signals. must be enabled using lasttog_en. note that the toggle position is common for all vertical signals. lasttog_b 13b optional fifth toggle position for the vertical signals. must be enabled using lasttog_en. note that the toggle position is common for all vertical signals. lasttog_c 13b optional fifth toggle position for the vertical signals. must be enabled using lasttog_en. note that the toggle position is common for all vertical signals. lasttog_d 13b optional fifth toggle position for the vertical signals. must be enabled using lasttog_en. note that the toggle position is common for all vertical signals. vseqalt_en 1b special v-sequence alternation mode is enabled when this register is programmed high. valt_map 1b enables the use of freeze/resume register locations to specify the valtsel0 and valtsel1 registers. must be enabled if vseqalt mode is enabled. valtsel0_even 18b select lines for special v-sequence alternation mode for even lines. used to concatenate vpat groups a/b/c/d into unique merged patterns. setting is used to specify one segment, with up to a maximum of 18 segments. valtsel1_even 18b select lines for special v-sequence alternation mode for even lines. used to concatenate vpat groups a/b/c/d into unique merged patterns. setting is used to specify one segment, with up to a maximum of 18 segments. valtsel0_odd 18b select lines for special v-sequence alternation mode for odd lines. used to concatenate vpat groups a/b/c/d into unique merged patterns. setting is used to specify one segment, with up to a maximum of 18 segments. valtsel1_odd 18b select lines for special v-sequence alternation mode for odd lines. used to concatenate vpat groups a/b/c/d into unique merged patterns. setting is used to specify one segment, with up to a maximum of 18 segments. spc_pat_en 1b enable special v-pattern to be inserted into one repetition of a vpata series. spc_pat_en [0]: set to 1 to enable vpatb to be used as special pattern insertion. spc_pat_en [1]: set to 1 to enable vpatc to be used as special pattern insertion. spc_pat_en [2]: set to 1 to enable vpatd to be used as special pattern insertion.
ad9927 rev. 0 | page 34 of 100 xv1 xv8 hd xv9 xv10 xv1 to xv8 use v-pattern group a xv9, xv10 use v-pattern group b 05892-036 figure 37. using separate group a and group b patterns xv1 xv24 hd v-pattern group a v-pattern group b v-pattern group c v-pattern group d 0 5892-037 figure 38. combining multiple v-patterns using concat_grp = 1 xv1 x v10 hd v-pattern group a v-pattern group b group a rep 1 group a rep 2 group a rep 3 05892-038 figure 39. combining group a and group b patterns with repetition group a/group b/group c/group d selection the ad9927 has the flexibility to use four different v-pattern groups in a vertical sequence. in general, the vertical outputs use the same v-pattern group during a particular sequence. it is possible to assign some of the outputs to a different v-pattern group, which can be useful in certain ccd readout modes. the groupsel registers are used to select group a, group b, group c, or group d for each v-output. in general, only a single v-pattern group is needed for the vertical outputs; therefore, group a should be selected for all outputs by default (groupsel_0, groupsel_1 = 0x00). in this configuration, all outputs use the v-pattern group specified by the vpatsela register. if additional flexibility is needed, some outputs can be set to group b, group c, or group d in the groupsel registers. in this case, those selected outputs use the v-pattern group specified by the vpatselb, vpatselc, or vpatseld registers. figure 37 shows an example where outputs v9 and v10 are using a separate v-pattern group b to perform special ccd timing. another application of the group a, group b, group c, and group d registers is to combine up to four different v-pattern groups together for more complex patterns. this is accom- plished by setting the concat_grp register (address 0x00, bits [13:10]) equal to 0x01. this setting combines the toggle positions from the v-pattern groups specified by registers vpatsela, vpatselb, vpatselc, and vpatseld for a
ad9927 rev. 0 | page 35 of 100 maximum of up to 16 toggle positions. example timing for the concat_grp = 1 feature is shown in figure 38. if only two groups are needed (up to eight toggle positions) for the specified timing, the vpatselb, vpatselc, and vpatseld registers can be programmed to the same value. if only three groups are needed, vpatselc and vpatseld can be programmed to the same value. following this approach conserves register memory if the four separate v-patterns are not needed. note that when concat_grp is enabled, the group a settings are used only for start position, polarity, length, and repetitions. all toggle positions for group a, group b, group c, and group d are combined together and applied using the settings in the vstarta, vpol_a, vlena, and vrepa registers. special vertical sequence alternation (svsa) mode the ad9927 has additional flexibility for combining four different v-pattern groups in a random sequence that can be programmed for specific ccd requirements. this mode of operation allows custom vertical sequences for ccds that require more complex vertical timing patterns. for example, using the special vertical sequence alternation mode, it is possible to support random pattern concatenation, with additional support for odd/even line alternation. figure 40 illustrates four common and repetitive vertical pattern segments, a through d, that are derived from the complete vertical pattern. figure 41 illustrates how each group can be concatenated together in an arbitrary order. to enable the svsa mode, write the vseqalt_en bit, address 0x20 bit [13], equal to 0x01. the location of the valtsel registers is shared with the vpat registers for xv24. when svsa mode is enabled, the valtsel register function is selected. to create svsa timing, divide the complete vertical timing pattern into four common and repetitive segments. identify the related segments as vpata, vpatb, vpatc, or vpatd. up to four toggle positions for each segment can be programmed using the v-pattern registers. table 15 shows how the segments are specified using a 2-bit representation. each bit from valtsel0 and valtsel1 are combined to produce four values, corresponding to patterns a, b, c, and d. table 15. valtsel bit settings for even and odd lines parameter valtsel bit settings valtsel0_even 0 0 1 1 valtsel1_even 0 1 0 1 valtsel0_odd 0 0 1 1 valtsel1_odd 0 1 0 1 resulting pattern for even lines a b c d resulting pattern for odd lines a b c d when the entire pattern is divided, program valtsel0 (even and odd) [17:0] and valtsel1 (even and odd) [17:0] so that the segments will be concatenated in the desired order. if separate odd and even lines are not required, set the odd and even registers to the same value. figure 42 illustrates the process of using six vertical pattern segments that have been concatenated into a small, merged pattern. program the register vrepa_1 to specify the number of segments that will be concatenated into each merged pattern. the maximum number of segments that can be concatenated to create a merged pattern is 18. program vlena, vlenb, vlenc, vlend to be of equal length. finally, program hblk to generate the proper h-clock timing using the procedure for hblk mode 2 described in the hblk mode 2 operation section. it is important to note that because the freeze/resume registers are used to specify the valtsel registers, the valt_map register must be enabled when using the special va lt m o d e . table 16. valtsel register locations 1 register function when vseqalt_en = 1 register location valtsel0_even [12:0] vseq register freeze1 [12:0] valtsel0_even [17:13] vseq register resume1 [17:13] valtsel1_even [12:0] vseq register freeze2 [12:0] valtsel1_even [17:13] vseq register resume2 [17:13] valtsel0_odd [12:0] vseq register freeze3 [12:0] valtsel0_ odd [17:13] vseq register resume3 [17:13] valtsel1_ odd [12:0] vseq register freeze4 [12:0] valtsel1_ odd [17:13] vseq register resume4 [17:13] 1 the valt_map register must be set to 1 to enable the use of valtsel registers.
ad9927 rev. 0 | page 36 of 100 xv1 xv2 xv23 vlena vlenb vlenc vlend v -pattern a xv3 v -p a ttern b v -p a ttern c v -p a ttern d notes 1. each segment must be the same length. vlena = vlenb = vlenc = vlend. 05892-039 figure 40. vertical timing divided into four segments: vpata, vpatb, vpatc, and vpatd hd combined v -pattern notes 1. able to concatenate patterns together arbitrarily. 2. each pattern can have up to four toggles programmed. 3. may concatenate up to 18 patterns into a merged pattern. 4. odd and even lines can have a different pattern concatenation specified by valtsel even and odd registers. ab b d a c c a bcbdabaa 05892-040 figure 41. concatenating each vpat group in arbitrary order notes 1. six v-pattern segments concatenated into a merged pattern. 2. common and repetitive vtp segments derived from the complete vtp pattern. 3. valtsel registers specify segment order to create the concatenated merged pattern. ac b d xv1 xv2 xv23 xv3 vpata vpatc vpatb vpatd vpatd vpata valtsel0_even 0 0 1 1 1 0 valtsel1_even 0 1 0 1 1 0 segment 1 a d xv1 to xv23 segment 2 segment 3 segment4 segment 5 segment 6 hd 0 5892-041 figure 42. example of special v-sequence alternation mo de using valtsel registers to specify segment order
ad9927 rev. 0 | page 37 of 100 using the lastreplen_en the lastreplen_en register (address 0x00, bits [19:16] in the sequence registers) is used to enable a separate pattern length to be used in the final repetition of several pulse repetitions. it is recommended that the lastreplen_en register bits be set high (enabled) and the lastreplen_a, lastreplen_b, lastreplen_c, and lastreplen_d registers be set to a value equal to the vlena, vlenb, vlenc, and vlend register values, respectively. generating line alternation for v-sequences and hblk during low resolution readout, some ccds require a different number of vertical clocks on alternate lines. the ad9927 can support this by using the vrep registers. this allows a different number of v-pattern group repetitions to be programmed on odd and even lines. only the number of repeats can be different in odd and even lines, while the v-pattern group remains the same. there are separate controls for the assigned group a, group b, group c, and group d patterns. all groups can support odd and even line alternation. group a uses the vrepa_1 and vrepa_2 registers; group b, group c, and group d use the corresponding vrep_odd and vrep_even registers. with the additional vrepa_3 and vrepa_4 registers, group a can also support 3-line and 4-line alternation. as discussed in the generating hblk line alternation section, the hblk signal can be alternated for odd and even lines. figure 43 shows an example of v-pattern group repetition alternation and hblk mode 0 alternation used together. xv1 xv2 xv24 hd hblk toge1 toge2 togo1 togo2 toge1 toge2 notes 1. the number of repeats for v-pattern groups a/b/c/d can be alternated on odd and even lines. 2. group a also supports 3- and 4-line alternation using the additional vrepa_3 and vrepa_4 registers. 3. the hblk toggle positions can be alte rnated between odd and even lines to generate different hblk patterns. vrepa_1 = 2 (or vrepb/c/d_even = 2) vrepa_2 = 5 (or vrepb/c/d_odd = 5) vrepa_1 = 2 (or vrepb/c/d_even = 2) 05892-042 figure 43. odd/even line alternation of v-patte rn group repetitions and hblk toggle positions
ad9927 rev. 0 | page 38 of 100 vertical masking using freeze/resume registers as shown in figure 44 and figure 45, the freeze/resume registers are used to temporarily mask the v-outputs. the pixel locations to begin the masking (freeze) and end the masking (resume) create an area in which the vertical toggle positions are ignored. at the pixel location specified in the freeze register, the v-outputs are held static at their current dc state, high or low. the v-outputs are held until the pixel location specified by the resume register is reached, at which point the signals continue with any remaining toggle positions, if any exist. four sets of freeze/resume registers are provided, allowing the vertical outputs to be interrupted up to four times in the same line. the freeze and resume positions 1 to 4 are enabled independently and applied to all groups (group a, group b, group c, and group d) using the vmask_en register. note that when masking is enabled, each group (group a, group b, group c, and group d) uses the same freeze/ resume positions. note that the freeze/resume registers are also used as the valtsel0 and valtsel1 registers during special vertical alternation mode. xv1 x v24 hd no masking area 0 5892-043 figure 44. no freeze/resume xv1 x v24 hd v-masking area freeze resume notes 1. all toggle positions within the freeze/resume masking area are ignored. h-counter continues to count during masking. 2. four separate masking areas are available, using freeze1/resume1, freeze2/resume2, freeze3/resume3, and freeze4/resume4 registers. 0 5892-044 figure 45. using freeze/resume
ad9927 rev. 0 | page 39 of 100 hold area using freeze/resume registers the freeze/resume registers can also be used to create a hold area in which the v-outputs are temporarily held and later continued, starting at the point where they were held. as shown in figure 46, this is different than the vmask_en register because the v-outputs continue from where they stopped rather than continuing from where they would have been. the hold area temporarily stops the pixel counter for the v-outputs, while the v-masking allows the counter to continue in the masking area. xv1 xv8 hd notes 1. when hold = 1 for any v-sequence group, the freeze and resume registers are used to specify the hold area. 2. above example: xv1 to xv10 are assigned to group a. hold bit for group a = 1. 3. h-counter for group a (xv1 to xv10) stops during hold area. xv9 hold area for group a xv10 freeze resume 05892-045 figure 46. hold area for group a
ad9927 rev. 0 | page 40 of 100 special pattern insertion additional flexibility is available using the spc_pat_en registers, which allows a group b, c, or d pattern to be inserted into a series of group a repetitions. this feature is useful when a different pattern is needed at the start, middle, or end of a sequence. figure 47 shows an example of a sweep region using vpata with multiple repetitions where a single repetition of vpatb has been added into the middle of the sequence. figure 48 shows more detail on how to set the registers to achieve the desired timing. note that vrepb is used to specify which repetition number has the special pattern inserted instead of vpata. vpatb always has priority over vpatc or vpatd if more than one spc_pat_en bit is enabled (spc_pat_en [0] has priority). vd xv1 to xvn hd region 1: sweep region line 0 line 1 region 0 region 2 line 24 line 25 line 2 scp1 scp2 pattern b inserted during pattern a repetitions 05892-046 figure 47. example of special pattern insertion x v1 hd v-pattern a v-pattern b v-pattern a rep 1 rep 2 rep n rep 5 rep 4 rep 3 register settings: description: spc_pat_en[0] = 1 v-pattern b is used as special pattern vrepa = n total number of reps used for sequence (n reps) vrepb = 4 rep 4 uses v-pattern b instead of v-pattern a notes 1. vstartb must be set equal to vstarta. 05892-047 figure 48. example of special pattern insertion, detail
ad9927 rev. 0 | page 41 of 100 complete field: co mbining v-sequences after the v-sequences are created, they are combined to create different readout fields. a field consists of up to nine regions, and within each region, a different v-sequence can be selected. figure 49 shows how the sequence change positions (scp) designate the line boundary for each region and how the seq registers then select which v-sequence is used in each region. registers to control the vsg outputs are also included in the field registers. table 17 summarizes the registers used to create the different fields. the seq registers, one for each region, select which of the v-sequences are active in each region. the mult_sweep registers, one for each region, are used to enable sweep mode and/or multiplier mode in any region. the scp registers create the line boundaries for each region. the vdlen register specifies the total number of lines in the field. the hdlen registers specifies the total number of pixels per line, and the hdlastlen register specifies the number of pixels in the last line of the field. the vpatsecond register is used to add a second v-pattern group to the xv1 to xv10 signals in the vertical sensor gate (vsg) line. the sgmask register is used to enable or disable each individual vsg output. there are two bits for each vsg output to enable separate masking in sgactline1 and sgactline2. setting a masking bit high masks the output; setting it low enables the output. the vsgpatsel register assigns one of the eight sg patterns to each vsg output. the individual sg patterns are created separately using the sg pattern registers. the sgactline1 register specifies which line in the field contains the vsg outputs. the optional sgactline2 register allows the same vsg pulses to be repeated on a different line. separate masking is not available for sgactline1 and sgactline2. table 17. field registers (clpob, pblk masking shown in table 10) register length range description seqx 5b 0 to 31 v-sequence no. selected v-sequence for each region in the field. mult_sweep 2b 0 to 3 enables multiplier mode and/or sweep mode for each region. 0: multiplier off, sweep off. 1: multiplier off, sweep on. 2: multiplier on, sweep off. 3: multiplier on, sweep on. scp 13b 0 to 8191 line no. sequence change position for each region. vdlen 13b 0 to 8191 lines total number of lines in each field. hdlastlen 13b 0 to 8191 pixels length in pixels of the last hd line in each field. vsgpatsel 24b high/low vsgpatsel selects which v-pattern toggle positions are used. when set to 0, toggle 1 and toggle 2 are used. when set to 1, toggle 3 and toggle 4 are used. [0]: xv1 selection (0 = use tog1, tog2; 1 = use tog3, tog4). [23]: xv24 selection. sgmask 24b high/low, each vsg set hi gh to mask each in dividual vsg output. [0]: xv1 mask. [23]: xv24 mask. sgactline1 13b 0 to 8191 line no. selects the line in the field where the vsg signals are active. sgactline2 13b 0 to 8191 line no. selects a second line in the field to repeat the vsg signals. if not used, set this equal to sgactline1 or to the maximum value.
ad9927 rev. 0 | page 42 of 100 vd region 0 field settings: 1. sequence change positions (scp0 to scp8) define each of the nine available regions in the field. 2. seq0 to seq8 select the desired v-sequence for each region. 3. sgactline1 register selects which hd line in the field contains the sensor gate pulse(s). xv1 to xvn hd scp1 scp2 seq0 seq1 scp3 seq2 scp4 seq3 scp5 seq4 scp8 seq8 region 1 region 2 region 3 region 4 region 8 vsg sgactline1 scp0 05892-048 figure 49. complete field is divided into regions vd xv1 to xvn hd region 1: sweep region line 0 line 1 region 0 region 2 line 24 line 25 line 2 scp1 scp2 05892-049 figure 50. example of sweep region for high speed vertical shift sweep mode operation the ad9927 contains an additional mode of vertical timing operation called sweep mode. this mode is used to generate a large number of repetitive pulses that span across multiple hd lines. an example of where this mode is needed is at the start of the ccd readout operation. at the end of the image exposure before the image is transferred by the sensor gate pulses, the vertical interline ccd registers should be free of all charge. this can be accomplished by quickly shifting out any charge using a long series of pulses from the vertical outputs. depending on the vertical resolution of the ccd, up to 3000 clock cycles might be needed to shift the charge out of each vertical ccd line. this operation spans across multiple hd line lengths. normally, the ad9927 vertical timing must be contained within one hd line length, but when sweep mode is enabled, the hd boundaries are ignored until the region is finished. to enable sweep mode within any region, program the appropriate sweep register to high. figure 50 shows an example of the sweep mode operation. the number of vertical pulses needed depends on the vertical reso- lution of the ccd. the toggle positions for the xv1 to xv24 signals are generated using the v-pattern registers (shown in table 13). a single pulse is created using the polarity and toggle position registers. the number of repetitions is then programmed to match the number of vertical shifts required by the ccd. repetitions are programmed into the v-sequence registers (shown in table 14) by using the vrep registers. this produces a pulse train of the appropriate length. normally, the pulse train is truncated at the end of the hd line length, but when sweep mode is enabled for this region, the hd boundaries are ignored. in figure 50, the sweep region occupies 23 hd lines. after the sweep mode region is complete, normal sequence operation resumes in the next region. when using sweep mode, be sure to set the region boundaries (using the sequence change positions) to the appropriate lines to prevent the sweep operation from overlapping the next v-sequence.
ad9927 rev. 0 | page 43 of 100 multiplier mode to generate very wide vertical timing pulses, a vertical region can be configured into a multiplier region. this mode uses the v-pattern registers in a slightly different manner. multiplier mode can be used to support unusual ccd timing requirements, such as vertical pulses that are wider than the 13-bit v-pattern toggle position counter. in general, the 13-bit toggle position counter can be used with the sweep mode feature to support very wide pulses; however, multiplier mode can be used to generate even wider pulses. the start polarity and toggle positions are still used in the same manner as the standard v-pattern group programming, but vlen is used differently. instead of using the pixel counter (hd counter) to specify the toggle position locations (vtog1, vtog 2, vtog 3, and vtog 4) of the v-pattern group, the vlen is multiplied with the vtog position to allow very long pulses to be generated. to calculate the exact toggle position, which is counted in pixels after the start position, use the following equation: vlen vtog position toggle mode multiplier = because the vtog register is multiplied by vlen, the resolution of the toggle position placement is reduced. if vlen = 4, the toggle position precision is reduced to 4-pixel increments instead of to single-pixel increments. table 18 summarizes how the v-pattern group registers are used in multiplier mode operation. in multiplier mode, the vrep registers must always be programmed to the same value as the highest toggle position. figure 51 illustrates this operation. the first toggle position is 2, and the second toggle position is 9. in nonmultiplier mode, this causes the v-sequence to toggle at pixel 2 and then at pixel 9 within a single hd line. however, in multiplier mode toggle positions are multiplied by the value of vlen (in this case, 4); therefore, the first toggle occurs at pixel 8, and the second toggle occurs at pixel 36. sweep mode has also been enabled to allow the toggle positions to cross the hd line boundaries. table 18. multiplier mode register parameters register length range description multi 1b high/low high enables multiplier mode. vpol 1b high/low starting polarity of xv1 to xv10 signals in each v-pattern group. vtog 13b 0 to 8191 pixel location toggle positions for xv1 to xv10 signals in each v-pattern group. vlen 13b 0 to 8191 pixels used as multip lier factor for toggle position counter. vrep 13b 0 to 8191 pixel location vrep_even/vrep_odd must be set to the same value as the highest vtog value. xv1 to xv24 hd vlen 1234123412341234123412341234123412341234 sta r t position of v pat group is still progr a mmed in the v -sequence registers pixel number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 3 55 4 1 2 4 2 multiplier mode v-pattern group properties: 1 start polarity (startpol = 0). 2 first, second, and third toggle positions (vtog1 = 2, vtog2 = 9). 3 length of vpat counter (vlen = 4); this is the minimum resolution for toggle position changes. 4 toggle positions o ccur at location equal to (vtog vlen). 5 if sweep region is enabled, the v-pulses may also cross the hd boundries, as shown above. 0 5892-050 figure 51. example of multiplier region for wide vertical pulse timing
ad9927 rev. 0 | page 44 of 100 vertical sensor gate (shift gate) patterns in an interline ccd, the vertical sensor gate (vsg) pulses are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers. from the light- shielded vertical registers, the image is clocked out line-by-line using the vertical transfer pulses (xv signals) in conjunction with the high speed horizontal clocks. the ad9927 has 24 vertical signals, and each signal can be assigned as a vsg pulse instead of an xv pulse. table 19 summarizes the vsg control registers, which are mostly located in the field registers space (see table 17). the vsgselect register (address 0x1c in the fixed address space) determines which vertical outputs are assigned as vsg pulses. when a signal is selected to be a vsg pulse, only the starting polarity and two of the v-pattern toggle positions are used. the vsgpatsel register in the sequence registers is used to assign either tog1 and tog2 or tog3 and tog4 to the vsg signal. note that only two of the four v-pattern toggle positions are available when a vertical signal is selected to be a vsg pulse. the sgactline1 and sgactline2 registers are used to select which line in the field is the vsg line. the vsg active line location is used to reference when the substrate clocking (subck) signal begins to operate in each field. for more information, see the substrate clock operation (subck) section. also located in the field registers, the sgmask register selects which individual vsg pulses are active in a given field. therefore, all sg patterns to be preprogrammed into the v-pattern registers and the appropriate pulses for the different fields can be enabled separately. the ad9927 is an integrated afetg + v-driver, so the connections between the afetg and v-driver are fixed, as shown in figure 53. the vsgselect must be programmed to 0xff8000. table 19. vsg control registers (also see field registers in table 17) register length range description 24b high/low selection of vsg signals from xv signals. set to 1 to make signal a vsg. [0]: xv1 selection (0 = xv pulse; 1 = vsg pulse). vsgselect (located in fixed address space, 0x1c) [1]: xv2 selection. [23]: xv24 selection. vsgpatsel 24b high/low when vsg signal is selected using the vsgselect register, vsgpatsel selects which v-pattern toggle positions are used. when set to 0, toggle 1 and toggle 2 are used. when set to 1, toggle 3 and toggle 4 are used. [0]: xv1 selection (0 = use tog1, tog2; 1 = use tog3, tog4). [1]: xv2 selection. [23]: xv24 selection. sgmask 24b high/low, each vsg set hi gh to mask each in dividual vsg output. [0]: xv1 mask. [23]: xv24 mask. sgactline1 13b 0 to 8191 line no. selects the line in the field where the vsg signals are active. sgactline2 13b 0 to 8191 line no. selects a second line in the field to repeat the vsg signals. if not used, set this equal to sgactline1 or to the maximum value. vd hd vsg pattern 4 12 3 programmable settings for each pattern: 1 start polarity of pulse (from vpol in sequence registers). 2 first toggle position (from v-pattern registers). 3 second toggle position (from v-pattern registers). 4 active line for vsg pulses within the field (from field registers). 05892-051 figure 52. vertical sensor gate pulse placement
ad9927 rev. 0 | page 45 of 100 internal vertical driver connections v1a v9 v10 v11 v12 v5 v4 xv4 xv22 (xsg7) xv5 xv23 (xsg8) f3 f4 v6 xv6 xv24 (xsg9) e4 v1b xv9 +3v v-driver xv10 xv11 xv12 xsubck xv16 (xsg1) xv1 xv17 (xsg2) j3 j4 d3 d5 d6 d7 k4 ad9927 3-level outputs 2-level outputs v2a v2b xv18 (xsg3) xv2 xv19 (xsg4) h3 h4 v7 v8 xv7 xv8 e3 d4 xsubcnt v13 v14 xv13 xv14 c7 c8 v3a v3b xv20 (xsg5) xv3 xv21 (xsg6) g4 g3 v15 xv15 d8 h10 internal timing generator vh, vl xsubcnt (logic input) subck (3-level output with xsubcnt) 05892-104 figure 53. internal afetg to v-driver connections
ad9927 rev. 0 | page 46 of 100 table 20. v1a output polarity vertical driver input xv1 xv16 (xsg1) v1a output l l vh l h vm h l vl h h vl table 21. v1b output polarity vertical driver input xv1 xv17 (xsg2) v1b output l l vh l h vm h l vl h h vl table 22. v2a output polarity vertical driver input xv2 xv18 (xsg3) v2a output l l vh l h vm h l vl h h vl table 23. v2b output polarity vertical driver input xv2 xv19 (xsg4) v2b output l l vh l h vm h l vl h h vl table 24. v3a output polarity vertical driver input xv3 xv20 (xsg5) v3a output l l vh l h vm h l vl h h vl table 25. v3b output polarity vertical driver input xv3 xv21 (xsg6) v3b output l l vh l h vm h l vl h h vl table 26. v4 output polarity vertical driver input xv4 xv22 (xsg7) v4 output l l vh l h vm h l vl h h vl table 27. v5 output polarity vertical driver input xv5 xv23 (xsg7) v5 output l l vh l h vm h l vl h h vl table 28. v6 output polarity vertical driver input xv6 xv24 (xsg8) v6 output l l vh l h vm h l vl h h vl table 29. v7 output polarity vertical driver input xv7 v7 output l vm h vl table 30. v8 output polarity vertical driver input xv8 v8 output l vm h vl table 31. v9 output polarity vertical driver input xv9 v9 output l vm h vl table 32. v10 output polarity vertical driver input xv10 v10 output l vm h vl
ad9927 rev. 0 | page 47 of 100 table 33. v11 output polarity vertical driver input xv11 v11 output l vm h vl table 34. v12 output polarity vertical driver input xv12 v12 output l vm h vl table 35. v13 output polarity vertical driver input xv13 v13 output l vm h vl table 36. v14 output polarity vertical driver input xv14 v14 output l vm h vl table 37. v15 output polarity vertical driver input xv15 v15 output l vm h vl table 38. subck output polarity vertical driver input xsubck xsubcnt subck output l l vh l h vh h l vmm h h vll
ad9927 rev. 0 | page 48 of 100 xv1 v1a x v16 (xsg1) vh vm vl 0 5892-105 figure 54. xv1, xv16, and v1a output polarities xv1 v1b x v17 (xsg2) vh vm vl 0 5892-106 figure 55. xv1, xv17, v1b output polarities xv2 v2a x v18 (xsg3) vh vm vl 0 5892-107 figure 56. xv2, xv18, v2a output polarities xv2 v2b x v19 (xsg4) vh vm vl 0 5892-108 figure 57. xv2, xv19, v2b output polarities
ad9927 rev. 0 | page 49 of 100 xv3 v3a x v20 (xsg5) vh vm vl 0 5892-109 figure 58. xv3, xv20, and v3a output polarities xv3 v3b x v21 (xsg6) vh vm vl 0 5892-110 figure 59. xv3, xv21, and v3b output polarities xv4 v4 x v22 (xsg7) vh vm vl 0 5892-111 figure 60. xv4, xv22, and v4 output polarities xv5 v5 x v23 (xsg8) vh vm vl 0 5892-112 figure 61. xv5, xv23, and v5 output polarities
ad9927 rev. 0 | page 50 of 100 xv6 v6 x v24 (xsg9) vh vm vl 0 5892-113 figure 62. xv6, xv24, and v6 output polarities xv7, x8, xv9, xv10 xv11, xv12, xv13, xv14, xv15 vm v 7, v8, v9, v10, v11, v12, v13, v14, v15 vl 05892-100 figure 63. 2-level v-driver output polarities xsubcnt subck xsubck vh vmm vll 05892-118 figure 64. xsubck, xsubcnt, and subck output polarities
ad9927 rev. 0 | page 51 of 100 mode registers the mode registers are used to select the field timing of the ad9927. typically, all of the field, v-sequence, and v-pattern information is programmed into the ad9927 at startup. during operation, the mode registers allow the user to select any com- bination of field timing to meet the requirements of the system. the advantage of using the mode registers in conjunction with preprogrammed timing is that it greatly reduces the system pro- gramming requirements during camera operation. only a few register writes are required when the camera operating mode is changed, rather than having to program all of the vertical timing information with each camera mode change. a basic still camera application can require six fields of vertical timingone for draft mode operation, one for autofocusing, and four for still image readout. all of the register timing information for the six fields is loaded at startup. then, during camera operation, the mode registers select which field timing is active, depending on how the camera is being used. table 39 shows how the mode registers are used. the mode register (address 0x2a) specifies how many total fields are used. any value from 1 to 7 can be selected using these three bits. the other two registers (0x2b and 0x2c) are used to select which of the programmed fields are used and in which order. up to seven fields can be used in a single mode write. the ad9927 starts with the field timing specified by field0, and on the next vd, switches to the timing specified by field1, and so on. after completing the total number of fields specified by mode, the ad9927 repeats by starting at the first field. this continues until a new write to the mode register occurs. figure 67 shows example mode register settings for different field configurations. note that only a write to address 0x2c properly resets the field counter. therefore, when changing the values in any of the mode registers, it is recommended that all three registers are updated together in the same field (vd period). caution the mode registers are sck updated by default. if they are configured as vd-updated registers by writing address 0xb4 = 0x03ff and address 0xb5 = 0xfc00, the new mode information is updated on the second vd falling edge after the write occurs, rather than on the first vd falling edge. see figure 66 for an example. table 39. mode registersvd updated address name length description 2a mode 3b total number of fields to cycle through. set from 1 to 7. 2b field0 5b selected field (from field registers in conf igurable memory) for the firs t field to cycle through. field1 5b selected field (from field registers in config urable memory) for the second field to cycle through. field2 5b selected field (from field registers in conf igurable memory) for the thir d field to cycle through. field3 5b selected field (from field registers in config urable memory) for the fourth field to cycle through. field4 5b selected field (from field registers in conf igurable memory) for the fifth field to cycle through. 2c field5 5b selected field (from field registers in conf igurable memory) for the sixth field to cycle through. field6 5b selected field (from field registers in config urable memory) for the seventh field to cycle through.
ad9927 rev. 0 | page 52 of 100 vd register write a mode field number 4 (draft) 4 (draft) 0 (still 1st field) example mode register change: register write a ?? write to mode registers 0x2a, 0x2b, 0x2c to specify change from draft mode (field4) to still mode (field0/1/2/3). also write to vga gain or any new register values needed for still frame operation, such as new field information. 1 (still 2nd field) 2 mode update mode write 0 5892-052 figure 65. update of mode regist er, sck updated (default setting) vd register write ab mode field number 4 (draft) 4 (draft) 0 (still 1st field) example mode register change: register write a ?? write to mode registers 0x2a, 0x2b, 0x2c to specify change from draft mode (field4) to still mode (field0/1/2/3). register write b ?? write to vga gain or any new register values needed for still frame operation, such as new field information. notes 1. new mode information is updated at second vd falling edge after serial write a. 1 (still 2nd field) 2 mode update mode write 05892-053 figure 66. update of mode register if changed to vd-updated register field3 field0 field1 field2 field5 field1 field4 field2 example 1: total fields = 3, first field = field0, second field = field1, third field = field2 mode settings: 0x2a = 0x3 0x2b = 0x820 0x2c = 0x0 example 2: total fields = 1, first field = field3 mode settings: 0x2a = 0x1 0x2b = 0x3 0x2c = 0x0 example 3: total fields = 4, first field = field5, second field = field1, third field = field4, fourth field = field2 mode settings: 0x2a = 0x4 0x2b = 0x11025 0x2c = 0x0 0 5892-054 figure 67. using the mode registers to select field timing
ad9927 rev. 0 | page 53 of 100 vertical timing example to better understand how the ad9927 vertical timing generation is used, consider the example ccd timing chart in figure 68. this example illustrates a ccd using a general 3-field readout technique. as described in the previous field section, each readout field must be divided into separate regions to perform each step of the readout. the sequence change positions (scp) determine the line boundaries for each region, and the seqx registers assign a particular v-sequence to each region. the v-sequences contain the specific timing information required in each region: v1 to v6 pulses (using v- pattern groups), hblk/clpob timing, and vsg patterns for the sg active lines. this timing example requires four regions for each of the three fields, labeled region 0, region 1, region 2, and region 3. because the ad9927 allows many individual fields to be pro- grammed, field0, field1, and field2 can be used to meet the requirements of this timing example. the four regions for each field are very similar in this example, but the individual registers for each field allow flexibility to accommodate other timing charts. region 0 is a high speed, vertical shift region. sweep mode can be used to generate this timing operation with the desired number of high speed vertical pulses needed to clear any charge from the ccds vertical registers. region 1 consists of only two lines and uses standard single- line, vertical shift timing. the timing of this region area is the same as the timing in region 3. region 2 is the sensor gate line where the vsg pulses transfer the image into the vertical ccd registers. this region might require the use of the second v-pattern group for the sg active line. region 3 also uses the standard single-line, vertical shift timing, the same timing as region 1. four regions are required in each of the three fields. the timing for region 1 and region 3 is essentially the same, reducing the complexity of the register programming. other registers need to be used during the actual readout operation. these include the mode registers, shutter control registers (primary_action, subck, gpo for mshut, and vsub control) and afe gain register. important note regarding signal polarities when programming the ad9927 to generate the v1 to v24 and subck signals, the external v-driver circuit usually inverts these signals. carefully check the required timing signals needed at the input and the output of the v-driver circuit being used and adjust the polarities of the ad9927 outputs accordingly.
ad9927 rev. 0 | page 54 of 100 vd hd v1 v 2 v5 v6 subck mshut vsub ccd out exposure ( t exp ) first field readout region 1 region 2 region 0 region 3 1 4 7 10 13 16 n?5 n?2 closed 2 5 8 11 14 17 20 n?4 n?1 open v3 v4 open 3 6 9 12 15 18 21 n?3 n region 1 region 2 region 0 region 3 region 1 region 2 region 0 region 3 second field readout third field readout field 0 field 1 field 2 0 5892-055 figure 68. ccd timing exampledividing each field into regions
ad9927 rev. 0 | page 55 of 100 shutter timing control the ad9927 supports the generation of electronic shuttering (subck) and also features flexible general-purpose outputs (gpo) to control mechanical shuttering, ccd substrate bias switching, and strobe circuitry. in the following documentation, the terms sense gate (sg) and vertical sense gate (vsg) are used interchangeably. substrate clock operation (subck) the ccd image exposure time is controlled by the substrate clock signal (subck), which pulses the ccd substrate to clear out accumulated charge. the ad9927 supports three types of electronic shuttering: normal, high precision, and low speed. along with the subck pulse placement, the ad9927 can accommodate different readout configurations to further suppress the subck pulses during multiple field readouts. the subck signal is a programmable string of pulses, each occupying a line following the primary sense gate active line, sgactline1 (registers are shown in table 40). the subck signal has programmable pulse width, line placement, and number of pulses to accurately control the exposure time. subck: normal operation by default, the ad9927 operates in the normal subck configuration, in which the subck signal is pulsing in every vd field (see figure 69). the subck pulse occurs once per line, and the total number of repetitions within the field determines the length of the exposure time. the subck pulse polarity and toggle positions within a line are programmable using the subck_pol and subck_tog1 registers (see table 40). the number of subck pulses per field is programmed in the subcknum register (address 0x75). as shown in figure 69, the subck pulses always begin in the line following the sg-active line, which is specified in the sgactline registers for each field. the subck_pol, subck_tog1, subck_tog2, subcknum, and subckstartline registers are updated at the start of the line after the sensor gate line, as described in the updating new register values section. subck: high precision operation high precision shuttering is used in the same manner as normal shuttering but uses an additional register to control the last subck pulse. in this mode, the subck still pulses once per line, but the last subck in the field has an additional subck pulse, whose location is determined by the subckhp_tog registers, as shown in figure 70. finer resolution of the exposure time is possible using this mode. leaving the subckhp_tog registers set to its maximum value (0xffffff) disables the last subck pulse (default setting). subck: low speed operation normal and high precision shutter operations are used when the exposure time is less than 1 field. for exposure times greater than 1 field, the low speed (ls) shutter features can be used. the ad9927 includes a field counter (primary field counter) to regulate long exposure times. the primary field counter must be activated (address 0x70) to serve as the trigger for the ls operation. the durations of the ls exposure and read are specified by the sgmask_num and subckmask_num register (address 0x74), respectively. as shown in figure 71, this mode suppresses the subck and vsg outputs for up to 8192 fields (vd periods). to activate an ls shutter operation, trigger the start of the exposure by writing to the primary_action register bits according to the desired effect. when the primary counter is activated, the next vd period becomes the first active period of the exposure for which the vsg and subck masks are applied. optionally, if the subckmask_skip1 register is enabled, the ad9927 ignores the first vsg and subck masks in the subsequent fields. this is generally desired so that the exposure time begins in the field after the exposure operation is initiated. figure 71 shows operation with subckmask_skip1 = 1. if the primary_action register is used while the subckmask_num and sgmask_num registers are set to 0, the behavior of the subck and vsg signals are not different from the normal shutter or high precision shutter operations. therefore, the primary field counter can be used for other tasks (described in the general-purpose outputs (gpos) section) without disrupting the normal activity. in addition, there exists a secondary field counter that has no effect on the subck and vsg signals. these counters are described in detail in the field counters section. subck start line by default, the subck pulses begin in the line following sgactline1. for applications where the subck pulse should be suppressed for one or more lines following the vsg line, the subckstartline register can be programmed. this register setting delays the start of the subck pulses until the specified number of lines following sgactline1. caution a value of 1 should not be used in the subckstartline register. a value of 0 is used to specify the subck pulses to begin in the next line after the sg line. a value of 2 is used to specify the subck pulses to begin two lines after the sg line, and so on.
ad9927 rev. 0 | page 56 of 100 read after exposure to read the ccd data after exposure, the sg should resume normal activity while the subck remains null. by default, the ad9927 generates the vsg pulses in every field. when only a single exposure and a single frame read is desired, such as is the case in the preview mode, the vsg and subck pulses can operate in every field. other applications require that a greater number of frames are read, in which case subck must be masked until the readout is finished. the subckmask_num register specifies the total number of fields (exposure and read) to mask subck. a 2-field ccd frame read mode typically requires two additional fields of subck masking (subckmask_num = 2). a 3-field, 6-phase ccd requires three additional fields of subck masking after the read begins (subckmask_num = 3). note that the subckmask_skip1 register setting allows subck pulses at the beginning of the field of exposure. table 40. subck and exposure/read register parameters register length range description sgmask_num 13b 0 to 8191 no. of fields exposure duration (number of fields to suppress vsg) for ls operation. subckmask_num 13b 0 to 8191 no. of fields exposure plus read out duration (number of fields to suppress subck) for ls. subckmask_skip1 1b on/off suppress sg/subck ma sks for one field (default = 0). typically set to 1. subckstartline 1 13b 0, 2 to 8191 line location line location to start the subck pulses, relative to sgline location. a value of 1 is invalid. see the subck start line section. subcknum 1 13b 1 to 8191 no. of pulses total number of subcks per field, at 1 pulse per line. must be ad9927 rev. 0 | page 57 of 100 vd subck subck programmable settings: 1. pulse polarity using the subck_pol register. 2. number of pulses within the field using the subcknum register (subcknum = 3 in the above example). 3. pixel location of pulse within the line and pulse width programmed using the subck1 toggle position registers. t exp vsg hd t exp 05892-056 figure 69. normal subck operation vd s ubck notes 1. second subck pulse is added in the last subck line. 2. location of second pulse is fully programmable using the subckhp t oggle position registers. vsg hd t exp t exp 0 5892-057 figure 70. high precision subck operation vd subck vsg trig g er exposure (0x70) t exp notes 1. subck can be suppressed for multiple fields by programming the exposure register to be greater than 0. 2. above example uses exposure = 1. 3. trigger register must also be used to start the low speed exposure. 4. vd/hd outputs can also be suppressed using the vdhdoff register = 1. 05892-058 figure 71. low speed subck operation
ad9927 rev. 0 | page 58 of 100 field counters the ad9927 contains three field counters (primary, secondary, and mode). when these counters are active, they increment with each vd cycle. the mode counter is the field counter used with the mode register to control the vertical timing signals, which was discussed in the mode registers section. the primary and secondary counters are more flexible and are generally used for shuttering signal applications. both the primary and secondary counters have several modes of operation that are dictated by address 0x70, including ? normal (single count) ? rapidshot (repeating count) ? shotdelay (delayed count) ? shotdelay with rapidshot ? manual exposure ? manual readout ? force to idle the primary counter regulates the expose and read actions by regulating the subck and vsg signals. in addition, if the rapidshot feature is used with the primary counter, the subck and vsg masking automatically repeats as necessary for multiple expose/read cycles. the secondary counter has no effect on the subck or vsg signal. both counters can be used to regulate the general-purpose signals described in the general-purpose outputs (gpos) section. table 41. primary/secondary field counter registers (address 0x70, address 0x71, and address 0x72) register length description primary_action 3b 0: idle, no counter action. gpo signals can still be controlled using polarity or gp_protocol = 1. second_action 3b 1: activate counter. single cycle of counter from 1 to counter maximum value, and then returns to idle state. 2: rapidshot. after reaching maximum counter value, counter wraps and repeats until reset. 3: shottimer: active single cycle of counter after added delay of n fields (use the corresponding delay register). 4: shottimer with rapidshot. same as 2, with added delay of n fields between each repetition. 5: manual exposure. primary counter stays in exposure until manual readout or reset to idle. this mode keeps the subck and vsg pulses masked indefinitely. 6: manual readout. primary counter switches to readout (vsg pulses becomes active). 7: force to idle. primary_max 13b primary counter maximum value. second_max 12b secondary counter maximum value. vdhd_mask 3b mask vd/hd during counter operation. primary_delay 13b shottimer. number of fields to delay before the next primary count (exposure) starts. if using shottimer with rapidshot, delay value is used between each repeat. primary_skip 1b when using shottimer with rapidshot, use primary delay valu e only before first count (exposure). second_delay 13b shottimer. number of fields to delay before the ne xt secondary count starts. if using shottimer with rapidshot, delay value is used between each repeat. second_skip 1b when using shottimer with rapidshot, use secondary delay value only before first count.
ad9927 rev. 0 | page 59 of 100 general-purpose outputs (gpo s ) the ad9927 provides programmable outputs to control a mechanical shutter, strobe/flash, the ccd bias select signal, or any other external component with general-purpose (gp) signals. eight gp signals, with up to four toggles each, are available that can be programmed and assigned to special gpo pins. these pins are bidirectional and allow visibility (as an output) and external control (as an input) of hblk, pblk, clpob, and outcontrol. the registers introduced in this section are described in table 4 2. gp toggles when configured as an output, each gpo1 to gpo8 output can deliver a signal that is the result of programmable toggle positions. the gp signals are independent and can be linked to either a specific vd period or over a range of vd periods via the primary or secondary field counters through the gp protocol register (address 0x73). as a result of their associations with the field counters, the gp toggles inherit the characteristics of the field counters, such as rapidshot and shotdelay. to use the gp toggles 1. program the toggle positions (address 0x7a to address 0xa9). 2. program the protocol (address 0x73). 3. program the counter parameters (address 0x71 to address 0x72). 4. activate the counter (address 0x70). for protocol 1 (no counter association), skip steps 3 and 4. with these four steps, the gp signals can be programmed to accomplish many common tasks. careful protocol selection and application of the field counters yields efficient results to allow the gp signals smooth integration with concurrent operations. note that the subck and vsg masks are linked to the primary counter; however, if their parameters are 0, the gpo can use the primary counter without expose/read activity. the secondary counter is independent and can be used simultaneously with the primary counter. some applications may require the use of both primary and secondary field counters with different gpo protocols, start times, and durations. such operations are easily handled by the ad9927. several simple examples of gpo applications using only one gpo and one field counter follow. these examples can be used as building blocks for more complex gpo activity. in addition, specific gpo signals can be passed through a 4-input lut to realize combinational logic between them. for example, gp1 and gp2 can be sent through an xor look-up table, and the result can be delivered on gp1, gp2, or both. also, either gp1 or gp2 can deliver their original toggles. table 42. gpo registers register length range description gp1_protocol 3b 0 to 7 0: idle. gp2_protocol 3b 0 to 7 1: no counter association, use manual_trig bits to enable each gp signal. gp3_protocol 3b 0 to 7 2: link to primary counter. gp4_protocol 3b 0 to 7 3: link to secondary counter. gp5_protocol 3b 0 to 7 4: link to mode counter (from vertical timing generation). gp6_protocol 3b 0 to 7 5: primary repeat (allows gp signals to repeat with rapidshot). gp7_protocol 3b 0 to 7 6: secondary repeat (allows gp signals to repeat with rapidshot). gp8_protocol 8b 0 to 7 7: keep on. manual_trig 8b off/on manual trigger for ea ch gp signal, for use with protocol 1. gp<1:8>_pol 8b low/high starting polarity for gp signals, only updated during protocol = 0. sel_gp<1:8> 8b off/on 1: select gp toggles visible at gpo1 to gpo8 when output is enabled (default); 0: select vertical signals visible at gpo4 to gpo8 when output is enabled. gpo4: subck. gpo5: xv21. gpo6: xv22. gpo7: xv23. gpo8: xv24. gpo_output_en 8b off/on 1: enable gpo1 to gpo8 outputs (one bit per output); 0: disable gpo1 to gpo8 outputs, pi ns will be high-z state (default). gp*_use_lut 8b off/on send gp signals through a programmable look-up table (lut). lut_for_gp12 4b logic setting desired logic to be realized on gp1 combined with gp2. lut_for_gp34 4b logic setting desired logic to be realized on gp3 combined with gp4.
ad9927 rev. 0 | page 60 of 100 register length range description lut_for_gp56 4b logic setting desired logic to be realized on gp5 combined with gp6. lut_for_gp78 4b logic setting desired logic to be realized on gp7 combined with gp8. example logic settings for lut_for_gpxy: 0x6 = gpy xor gpx (see figure 77). 0x7 = gpy nand gpx. 0x8 = gpy and gpx. 0xe = gpy or gpx. gp*_tog*_fd 13b 0 to 8191 field field of activity, relative to primary and secondary counter for corresponding toggle. gp*_tog*_ln 13b 0 to 8191 line line of activity for corresponding toggle. gp*_tog*_px 13b 0 to 8191 pixel pixel of activity for corresponding toggle. gpo_int_en 1b off/on when set to 1, intern al signals are viewable on gpo5 to gpo8. gpo5: outcontrol. gpo6: hblk. gpo7: clpob. gpo8: pblk.
ad9927 rev. 0 | page 61 of 100 single-field toggles single-field toggles occur in the next field only. there can be up to four toggles in the field. the mode is set with gp_protocol equal to 1, and then the toggles are triggered in the next field by writing to the manual_trig register (0x70 [13:6]). in this mode, the field toggle settings must be set to a value of 1. two consecutive fields do not have activity. if toggles are required to repeat in the next field, the manual_trig register can be written to in consecutive fields. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x7a ? 0x000a001 0x7b ? 0x0002000 0x7c ? 0x000000f 0x7d ? 0x00c4002 0x7e ? 0x0004000 0x7f ? 0x00000b3 details a) field 0: 0x70 ? 0x0000040 0x73 ? 0x0000001 b) field 1: 0x73 ? 0x0000000 vd 1 register write ab gp1_protocol 0 1 0 gpo1 notes 1. the field toggle position must be set to 1 when gp protocol is 1. caution! the gp_protocol must be reset before using again. 05892-059 figure 72. single-field toggles using gp_protocol = 1 scheduled toggles scheduled toggles are programmed to occur during any upcoming field. for example, there can be one toggle in field 1, two toggles in field 3, and a last toggle in field 4. the mode is set with gp_protocol = 2 or gp_protocol = 3. mode 2 tells the gpo to obey the primary field counter, and mode 3 tells the gpo to obey the secondary field counter. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x7a ? 0x00c4002 0x7b ? 0x0004000 0x7c ? 0x00000b3 details a) field 0: 0x70 ? 0x0000008 0x73 ? 0x0000003 vd 1 2 register write a gp1_protocol 0 secondary count 01 3 20 gpo1 caution! the primary counter regulates the subck and vsg activity. link a gpo to the primary counter only if it is to happen during exposure/read. (idle) 0 5892-060 figure 73. scheduled toggles using gp_protocol = 3
ad9927 rev. 0 | page 62 of 100 rapidshot sequences rapidshot technology provides continuous repetition of scheduled toggles. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x71 ? 0x0004000 0x7a ? 0x000a001 0x7b ? 0x0002000 0x7c ? 0x000000f 0x7d ? 0x00c4002 0x7e ? 0x0004000 0x7f ? 0x00000b3 0x73 ? 0x0000006 details a) field 0: 0x70 ? 0x0000010 b) field 2: 0x70 ? 0x0000007 vd 12345 register write ab gp1_protocol 06 0(idle) 1 2 1 2 1 0 gpo1 terminated at vd edge notes 1. the gp protocols are the same as the scheduled toggles, except the toggles can be excluded from repetition by choosing gp protocol 2 or 3. caution! the field counter must be forced into idle state to terminate repetitions. secondary count 05892-062 figure 74. rapidshot toggle operation using gp_protocol = 6 shotdelay sequences shotdelay technology provides internal delay of scheduled toggles. the delay is in terms of fields. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x71 ? 0x0004000 0x72 ? 0x000c000 0x7a ? 0x000a001 0x7b ? 0x0002000 0x7c ? 0x000000f 0x73 ? 0x0000003 details a) field 0: 0x70 ? 0x0000018 vd 1 2 register write a gp1_protocol 03 0(idle) 1 2 3 1 2 0 gpo1 secondary count 05892-063 figure 75. shotdelay toggle operation using gp_protocol = 3
ad9927 rev. 0 | page 63 of 100 gp look-up tables (lut) the ad9927 is equipped with a look-up table for each pair of consecutive gp signals when configured as outputs. gp1 is always combined with gp2, gp3 is always combined with gp4, gp5 is always combined with gp6, and gp7 is always combined with gp8. the external gpo outputs from each pair can output the result of the lut or the original gp internal signal. gp1 lut 1 0 0 1 gpo2 gpo1 gp2 gp2_use_lut gp1_use_lut 0 5892-064 figure 76. internal lut for gp1 and gp2 signals address 0x79 dictates the behavior of the lut and which signals receive the result. each 4-bit lut_for_gpxy register can realize any logic combination of gpx and gpy. for example, table 43 shows how the register values of lut_for_gp12 [11:8] are determined. xor, nand, and, and or results are shown, but any 4-bit combination is possible. a simple example of xor gating is shown in figure 77. table 43. lut results based on gp1, gp2 values gp2 gp1 lut: xor lut: nand lut: and lut: or 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 1 gp1 gp2 gpo2 notes 1. logic combination (xor) of programmed toggles gp1 and gp2. lut_for_gp12[11:8] = 0x06 gp2_use_lut = 1 gp1_use_lut = 0 gpo1 05892-065 figure 77. lut example for gp1 xor gp2 field counter and gpo limitations the following is a summary of the known limitations of the field counters and gpo signals that dictate usability. ? the field counter trigger (primary_action and secondary_action registers, address 0x70) is self-reset at the start of every vd period. therefore, there must be one vd period between sequential programming to that address. ? if gp*_protocol = 1, it must be manually reset to gp*_protocol = 0 one vd period before it can be used again. if manual toggles are desired in sequential fields, the manual_trig register should be used in conjunction with gp*_protocol = 1.
ad9927 rev. 0 | page 64 of 100 complete exposure/readout operation using primary counter and gpo signals figure 78 demonstrates a typical expose/read cycle while exercising the gpo signals. using a 3-field ccd with an exposure time that is greater than one field but less than two fields in duration, requires a total of five fields for the entire exposure/readout operation. other exposure times and other ccd field config- urations require modification of these example settings. note that if the mode registers are changed to be vd updated, as shown in the mode registers section and in figure 66, the mode update will be delayed by one additional field. this should be accounted for in selecting the number of fields to cycle and which vd location to write to the mode registers. 1. the primary counter is used to control the masking of vsg and subck during exposure/readout. the primary_max register should be set equal to the total number of fields used for exposure and readout. in this example, primary_max = 5. the subck masking should not occur immediately at the next vd edge (step 2), because this would define an exposure time that begins in the previous field. write to the primary_delay register to delay the masking of vsg and subck pulses in the first exposure field. in this example, maskdelay = 1. write to the subckmask_num register (address 0x74) to specify the number of fields to mask subck while the ccd data is read. in this example, subckmask_num = 4. write to the sgmask_num register (address 0x74) to specify the number of fields to mask vsg outputs during exposure. in this example, sgmask_num = 1. write to the primary_action register (address 0x70) to trigger the gp1 (strobe), gp2 (mshut), and gp3 (vsub) signals and to start the expose/read operation. write to the mode registers to configure the next five fields. the first two fields during exposure are the same as the current draft mode fields, and the following three fields are the still-frame readout fields. the register settings for the draft mode field and the three readout fields are previously programmed. note that if the mode registers are changed to vd updated, only one field of exposure should be included (the second one) because the mode settings will be delayed an extra field. 2. vd/hd falling edge updates the serial writes from 1. 3. gp3 (vsub) output turns on at the field/line/pixel specified. vsub example 1 and example 2 use gp3tog1_fd = 1. 4. gp1 (strobe) output turns on and off at the location specified. 5. gp2 (mshut) output turns off at the location specified. 6. the next vd falling edge automatically starts the first read field. 7. the next vd falling edge automatically starts the second read field. 8. the next vd falling edge automatically starts the third read field. 9. write to the mode register to reconfigure the single draft mode field timing. note that if the mode registers are changed to vd updated, this write should occur one field earlier. 10. vd/hd falling edge updates the serial writes from 9. vsg outputs return to draft mode timing. subck output resumes operation. gp2 (mshut) output returns to the on position (active or open). gp3 (vsub) output returns to the off position (inactive).
ad9927 rev. 0 | page 65 of 100 vd subck vsub (gpo3) mechanical shutter open closed example 1 example 2 mshut (gpo2) strobe (gpo1) serial writes open vsg still image readout ccd out draft image still image first field still image second field still image third field draft image draft image 1 9 2 4 3 5 67810 10 10 10 t exp primary count 1 2 3 4 5 0 (idle) 0 0 0 5892-066 figure 78. complete exposure/readout operation using primary counter and gpo signals
ad9927 rev. 0 | page 66 of 100 manual shutter operation using enhanced sync modes the ad9927 also supports an external signal to control exposure, using the sync input. generally, the sync input is used as an asynchronous reset signal during master mode operation. when the enhanced sync mode is enabled, the sync input provides additional control of the exposure operation. normal sync mode (mode 1) by default, the sync input is used in master mode for synchronizing the internal counters of the ad9927 with external timing. the sync during master mode operation section describes how horizontal, vertical, and field designator signals are reset by the rising edge of the sync pulse. figure 79 also shows how this mode operates, highlighting the behavior of the mode field designator. enhanced sync modes (modes 2 and 3) the enhanced sync modes can be used to accommodate unique synchronization requirements during exposure operations. in sync mode 2, the v and vsg outputs are suspended and the vd output is masked. the v-outputs are held at the dc value established by the sequence 0 start polarities. there is no scp operation, but the h-counter is still enabled. finally, the afe sampling clocks, hd, h/rg, clpob, hblk, are operational and use sequence 0 behavior. see figure 80 for more details. to enable the enhanced sync modes, set the register enh_sync_en (address 0x13 bit [3]) to 1. mode 3 uses all of these features, but the v-outputs are continuous through the sync pulse interval. vd control pulses are masked during the sync interval, and the hd pulse can also be masked, if required (see figure 81). it is important to note that in both of these enhanced modes, the sync pulse resets the counters at both the falling edge and the rising edge of the sync pulse. register update and field designator when using special sync mode 2 or 3, the vd-updated registers, such as primary_action, are not updated during the sync interval, and the scp0 function is ignored and held at 0 (see figure 82). when using either sync mode 2 or 3, both the rising and falling edges increment the internal field designator; therefore, the new register data takes effect and vtp information is updated to new seq0 data. however, this does not occur if the mode register is to create an output of one field. in that case, the region, sequence, and group information does not change (see figure 83). shutter operation in slr mode referring to figure 84, 1. to turn on vsub, write to the appropriate gp registers to trigger vsub and start the manual exposure [primary_action = 5]. this change takes effect after the next vd, and subck is suppressed during the exposure and readout phases. 2. to turn on mshut during the interval between the next vd and sync, write to the appropriate gp register. when mshut is in the on position, it has line and pixel control. this change takes effect on the sync falling edge since there is an internal vd. 3. if the mode register is programmed to cycle through multiple fields (5, 7, 3, 5, 7, 3, , in this example), the internal field designator increments. if the mode register is not required to increment, set up the mode register such that it outputs only one field. this prevents the mode counter from incrementing during the sync interval. 4. write to the manual readout trigger to begin the manual readout [primary_action = 6]. write to the appropriate gp registers to trigger mshut to toggle low at the end of the exposure. this change takes effect on the sync rising edge during readout. since vd register update is disabled, the trigger takes effect on the sync rising edge. the mshut falling edge is aligned to the sync rising edge. because the mshut falling edge is aligned with vd, it may be necessary to insert a dummy vd to delay the readout. note that since the internal exposure counter (primary counter) is not used during manual sync mode operation and the vd register update is disabled, control is lost on the fine placement of the gp signals for vsub, mshut, and strobe edges while sync is low. new serial registers sync modes 2 and 3 are controlled using the registers listed in table 44. table 44. registers for enhanced sync modes register length description enh_sync_en 1b hi active to enable (default lo) sync_mask_v 1b hi active to enable masking (default lo) sync_mask_vd 1b hi active to enable masking (default hi) sync_mask_hd 1b hi active to enable masking (default hi) note that registers for enhanced sync modes are located at address 0x13 bits [6:3].
ad9927 rev. 0 | page 67 of 100 vd hd suspend sync 73 5 notes 1. the sync rising edge resets vd/hd and counters to 0. 2. sync polarity is programmable using syncpol register (addr 0x13). 3. during sync low, all internal counters are reset and vd/hd can be suspended using the syncsuspend register (addr 0x13). 4. the sync rising edge causes the internal field designator to increment. 5. if syscsuspend = 1, vertical clocks, h1 to h4, and rg are held at the same polarity specified by outcontrol = low. 6. if syncsuspend = 0, all clock outputs continue to operate normally until sync reset edge. field designator h1 to h4, rg, xv1 to xv24 vsg, subck 0 5892-083 figure 79. default mode 1 5 1 2 3 4 1 falling edge resyncs the circuit to the line/pixel number 0. vd and hd internally resync. 2 rising edge resets counters. 3 vd is disabled during sync. the register is programmable. 4 scp, hblk, and clpob are held at seq0 value. 5 xv1 to xv24 signals are held at the v-output start polarity. sync vd vdlen hd scp x v1 to xv24 05892-084 figure 80. enhanced sync mode 2 with ve rtical signals held at vtp start value
ad9927 rev. 0 | page 68 of 100 1 2 3 1 sync_mask_vd is a new register. hi will mask vd. default = hi. 2 sync_mask_hd is a new register. hi will mask hd. default = lo. 3 v-output pulses continue in sequence. vdlen sync vd hd scp xv1 to xv24 05892-085 figure 81. enhanced sync mode 3 111 111 notes 1. vd-updated registers (for example, primary_action) are disabled during the sync interval. sync vd 1 vd registers are updated here. 05892-086 figure 82. register update behavior 5 1 field designator is incremented on both sync edges. 57 3 7 sync vd field designator 1 1 05892-087 figure 83. special sync mode effect on field designator
ad9927 rev. 0 | page 69 of 100 57 3 57 3 37 5 1 see the shutter operation in slr mode section. 2 see the shutter operation in slr mode section. 3 see the shutter operation in slr mode section. 4 see the shutter operation in slr mode section. 5 subck output is suppressed during exposure and readout when exposure trigger is used. sync vd field designator v-outputs mshut vsub draft exposure dummy field readout odd readout even draft 1 4 2 3 5 5 05892-088 figure 84. enhanced sync modeman ual shutter operation, slr mode
ad9927 rev. 0 | page 70 of 100 analog front-end description and operation 6db ~ 42db ccdin cli digital filter clpob dc restore optical black clamp 12-bit adc vga dac cds internal v ref 2v full scale precision timing generation shp shd 1.2v output data latch reft refb v-h timing generation shp shd doutphase clpob pblk 0.4v 1.4v ad9927 0.1f vga gain register 0.1f 0.1f clamp level register 12 pblk ?3db, 0db, +3db, +6db pblk pblk (when dcbyp = 1) shp s1 1 s2 1 blank to zero or clamp level 1 s1 is normally closed; s2 is normally open. cds gain register vd hd dout doutphase dclk dclk mode fixed delay cli 1 0 dclkinv 05892-067 figure 85. analog front-end functional block diagram the ad9927 signal processing chain is shown in figure 85. each processing step is essential for achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.2 v, making it compatible with the 1.8 v core supply voltage of the ad9927. the dc restore switch is active during the shp sample pulse time. the dc restore circuit can be disabled when the optional pblk signal is used to isolate large-signal swings from the ccd input (see analog preblanking). bit [6] of afe register address 0x00 controls whether the dc restore is active during the pblk interval. analog preblanking during certain ccd blanking or substrate clocking intervals, the ccd input signal to the ad9927 can increase in amplitude beyond the recommended input range. the pblk signal can be used to isolate the cds input from large-signal swings. while pblk is active (low), the cds input is internally shorted to ground. note that because the cds input is shorted during pblk, the clpob pulse should not be used during the same active time as the pblk pulse. correlated double sampler (cds) the cds circuit samples each ccd pixel twice to extract the video information and to reject low frequency noise. the timing shown in figure 20 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and data level of the ccd signal, respectively. the placement of the shp and shd sampling edges is determined by the setting of the shploc and shdloc registers located at address 0x37. placement of these two clock signals is critical for achieving the best performance from the ccd. the cds gain is variable in three steps by using the afe address 0x04: ?3 db, 0 db (default), and +3 db. improved noise performance results from using the +3 db setting, but the input range will be reduced (see analog specifications).
ad9927 rev. 0 | page 71 of 100 variable gain amplifier the vga stage provides a gain range of approximately 6 db to 42 db, programmable with 10-bit resolution through the serial digital interface. a gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when compared to 1 v full-scale systems, the equivalent gain range is 0 db to 36 db. the vga gain curve follows a linear-in-db characteristic. the exact vga gain is calculated for any gain register value by db 75 . 5 ) 0358 . 0 ( (db) + = code gain where code is the range of 0 to 1023. vga gain register code v g a gain (db) 42 36 30 24 18 12 6 0 127 255 383 511 639 767 895 1023 05892-068 figure 86. vga gain curve adc the ad9927 uses a high performance adc architecture optimized for high speed and low power. differential non- linearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. see figure 5 and figure 7 for typical linearity and noise performance plots for the ad9927. optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccds black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level register. the value can be programmed between 0 lsb and 255 lsb in 1023 steps. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a dac. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during postprocessing, the ad9927 optical black clamping can be disabled using bit d2 in the afe register address 0x00. when the loop is disabled, the clamp level register can still be used to provide fixed offset adjustment. note that if the clpob loop is disabled, higher vga gain settings reduce the dynamic range because the uncorrected offset in the signal path is gained up. the clpob pulse should be aligned with the ccds optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide. shorter pulse widths can be used, but the ability for the loop to track low frequency variations in the black level will be reduced. see the horizontal clamping and blanking section for timing examples. digital data outputs the ad9927 digital output data is latched using the rising edge of the doutphase register value, as shown in figure 85. output data timing is shown in figure 21 and figure 22. it is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the adc. programming the afe register address 0x01, bit d1, to 1 sets the output latches to transparent. the data outputs can also be disabled (three-stated) by setting the afe register address 0x01, bit d0, to 1. the dclk output can be used for external latching of the data outputs. by default, the dclk output tracks the values of the doutphase registers. by changing the dclkmode register, the dclk output can be held at a fixed phase, and the doutphase register values are ignored. the dclk output can also be inverted with respect to dout, using the dclkinv register bit. the switching of the data outputs can couple noise back into the analog signal path. to minimize switching noise, it is recommended that the doutphase registers be set to the same edge as the shp sampling location, or up to 15 edges after the shp sampling location. other settings can produce good results, but experimentation is necessary. it is recommended that the doutphase location not occur between the shd sampling location and 15 edges after the shd location. for example, if shdloc = 0, doutphase should be set to an edge location of 16 or greater. if adjustable phase is not required for the data outputs, the output latch can be left transparent using address 0x01, bit d1. the data output coding is normally straight binary, but the coding can be changed to gray coding by setting the afe register address 0x01, bit d2, to 1.
ad9927 rev. 0 | page 72 of 100 power-up sequence for master mode when the ad9927 is powered up, the following sequence is recommended (refer to figure 87 for each step). note that a sync signal is required for master mode operation. if an external sync pulse is not available, it is possible to generate an internal sync event by writing to the swsync register. 1. turn on the power supplies for ad9927 and start the master clock, cli. 2. reset the internal ad9927 registers by writing 1 to the sw_rst register (address 0x10). 3. by default, vertical outputs v1 to v24 are low. if necessary, write to the standby3 output polarity (address 0x26) to set different polarities for the vertical outputs in order to avoid damage to the v-driver and ccd. write to address 0x1c to configure each v-output as a vertical transfer clock (xv) or sensor pulse (vsg). 4. power-up the v-driver supplies, vh and vl, anytime after step 3 is complete to set the proper polarities. 5. load the required registers to configure the necessary vertical timing, horizontal timing, high speed timing, and shutter timing. set the recommended start-up address 0xd8 to 0x888. 6. to place the part into normal power operation, write 0x04 to register 0x00. this sets the standby register (afe register address 0x00, bits [1:0]) to normal operation and enables the ob clamp (afe register address 0x00, bit [2]). if the clo output is being used to drive a crystal, also power up the clo oscillator by writing 1 to address 0x15. 7. by default, the internal timing core is held in a reset state, with tgcore_rstb register = 0. write 1 to the tgcore_rstb register (address 0x14) to start the internal timing core operation. note if a 2 clock is used for the cli input, the clidivide register (0x0d) should be set to 1 before resetting the timing core. 8. configure the ad9927 for master mode timing by writing 1 to the master register (address 0x20). 9. write 1 to the outcontrol register (address 0x11). this allows the outputs to become active after the next sync rising edge. normally outcontrol takes effect after the next vd edge; however, because the part is just being powered up, there is no vd edge until the rising edge of the sync signal. write 0xff8000 to the vsgselect register to properly configure the sensor gate signals. 10. generate a sync event. if sync is high at power-up, bring the sync input low for a minimum of 100 ns, and then bring sync high again. this causes the internal counters to reset and starts vd/hd operation. the first vd/hd edge allows vd-updated register updates to occur, including outcontrol to enable all outputs. if a hardware sync is not available, the swsync register (address 0x13, bit [14]) can be used to initiate a sync event.
ad9927 rev. 0 | page 73 of 100 power supplies serial writes vd (output) 1h first field sync (input) cli (input) hd (output) h-clocks v1 to v24 subck t sync 0v vh supply for v-driver vl supply for v-driver hi-z by default hi-z by default low by default hi-z by default 4 23 5 67 89 10 1v h2, h4, h6, h8 h1, h3, h5, h7, rg clocks active when outcontrol register is updated at vd/hd edge 05892-069 figure 87. recommended power-up sequen ce and synchronization, master mode
ad9927 rev. 0 | page 74 of 100 table 45. power-up register write sequence address data description 0x10 0x01 reset all registers to default values 0x26 user- defined standby3 vertical output polarities 0x20 to 0xfff user- defined horizontal, vertical, shutter timing 0xd8 0x888 configure start-up register 0x00 0x04 power-up the afe, enables ob clamp 0x15 0x01 starts clo oscillator (if using crystal) 0x14 0x01 starts internal timing core 0x20 0x01 configure for master mode 0x11 0x01 enable all outputs after sync 0x1c 0xff8000 configure sensor gate signals 0x13 0x4xx1 swsync (if using software sync) using the swsync register if an external sync pulse is not available, it is possible to generate an internal sync in the ad9927 by writing 1 to the swsync register (address 0x13, bit [14]). if the software sync option is used, the sync input (pin d3) should be low (v ss ) during power-up. the syncenable register (address 0x13, bit [0]) should be set high. sync during master mode operation the hardware sync input can be used anytime during operation to synchronize the ad9927 counters with external timing, as shown in figure 88. the operation of the digital outputs can be suspended during the sync operation by setting the syncsuspend register (address 0x13, bit [2]) to 1. if syncsuspend = 1, the polarities of the outputs are held at the same state as outcontrol = low, as shown in table 46. power-up and synchronization in slave mode the power-up procedure for slave mode operation is the same as the procedure for master mode operation with two exceptions: ? eliminate step 8. do not write the part into master mode. ? no sync pulse is required in slave mode. substitute step 10 with starting the external vd and hd signals. this synchronizes the part, allows the register updates, and starts the timing operation. when the ad9927 is used in slave mode, the vd/hd inputs are used to synchronize the internal counters. after a falling edge of vd, there is a latency of 36 master clock cli edges after the falling edge of hd until the internal h-counter is reset. the reset operation is shown in figure 89. additional restrictions in slave mode when operating in slave mode, the following restrictions should be noted: ? the hd falling edge should be located in the same cli clock cycle as the vd falling edge, or later than the vd falling edge. the hd falling edge should not be located within five cycles prior to the vd falling edge. ? if possible, all start-up serial writes should be performed with vd and hd disabled. this prevents unknown behavior caused by partial updating of registers before all information is loaded. vd hd suspend sync h1 to h4, rg, xv1 to xv24, vsg, subck notes 1. the sync rising edge resets vd/hd and counters to 0. 2. sync polarity is programmable using syncpol register (addr 0x13). 3. during sync low, all internal counters are reset and vd/hd can be suspended using the syncsu spend register ( addr 0x13). 4. if syncsuspend = 1, vertical clocks, h1 to h4, and rg are held at the same polarity specified by outcontrol = low. 5. if syncsuspend = 0, all clock outputs continue to operate normally until the sync reset edge. 05892-070 figure 88. sync timing to synchronize the ad9927 with external timing
ad9927 rev. 0 | page 75 of 100 vd hd cli xx xxxx x x 3ns min xx x xxx x xx x xxx 3ns min t clidly 35.5 cycles xx x 0 x x x x xx x xx xx x x 12 notes 1. external hd falling edge is latched by cli rising edge, and then latched again by shd internal falling edge. 2. internal h-counter is always reset 35.5 clock cycles after the internal hd falling edge. 3. depending on the value of shdloc, h-counter reset can occur 36 or 37 cli clock edges after the external hd falling edge. 4. shdloc = 0 is shown in above example. in this case, the h-counter reset occurs 36 cli rising edges after hd falling edge. 5. hd falling edge should occur coincident with vd falling edge (within same cli cycle) or after vd falling edge. hd falling edge should not occur within five cli cycles prior to the vd falling edge. h-counter reset shd internal hd internal h-counter (pixel counter) t vdhd 0 5892-071 figure 89. external vd/hd and internal h-counter synchronization, slave mode 1 hblktog1 60 (60 ? 36) = 24 2 hblktog2 100 (100 ? 36) = 64 3 clpob_tog1 103 (103 ? 36) = 67 4 clpob_tog2 112 (112 ? 36) = 76 master mode slave mode h1 clpob pixel no. hd 112 103 100 60 0 12 3 4 0 5892-072 figure 90. example of slave mode register setting to obtain desired toggle positions vertical toggle position placement near counter reset an additional consideration during the reset of the internal counters is the vertical toggle position placement. prior to the internal counters being reset, there is a region of 36 pixels during which no toggle positions should be programmed. as shown in figure 91, for master mode the last 36 pixels before the hd falling edge must not be used for toggle position placement of the v, vsg, subck, hblk, pblk, or clpob pulses. figure 92 shows the same example for slave mode. the same restriction applies: the last 36 pixels before the counters are reset cannot be used. however, in slave mode, the counter reset is delayed with respect to vd/hd placement, so the inhibited area is different than it is in master mode. it is recommended that pixel location 0 not be used for any of the toggle positions for the vsg and subck pulses.
ad9927 rev. 0 | page 76 of 100 01234 vd hd x x x x n n?1 n?2 n?3 n?4 n?5 n?6 n?7 n?8 n?9 n?10 n?11 n?12 n?13 n?32 n?33 n?34 n?35 h-counter reset notes 1. toggle positions cannot be programmed within 36 pixels of pixel 0 location. h-counter (pixel counter) no toggle positions allowed in this area 05892-073 figure 91. toggle position inhibited areamaster mode n?1 n012 vd hd n?2 n?3 n?4 no toggle positions allowed in this area n?5 n?6 n?7 n?8 n?9 n?10 n?11 n?12 n?13 n?32 n?33 n?34 n?35 x x x x x x notes 1. toggle positions cannot be programmed within 36 pixels of pixel 0 location. h-counter (pixel counter) h-counter reset 05892-074 figure 92. toggle position inhibited areaslave mode standby mode operation the ad9927 contains three standby modes to optimize the overall power dissipation in a particular application. bits [1:0] of address 0x00 control the power-down state of the device: ? standby [1:0] = 0 = normal operation (full power) ? standby [1:0] = 1 = standby1 mode ? standby [1:0] = 2 = standby2 mode ? standby [1:0] = 3 = standby3 mode (lowest power) table 46 summarizes the operation of each power-down mode. the outcontrol register takes priority over the standby1 and standby2 modes in determining the digital output states, but standby3 mode takes priority over outcontrol. standby3 has the lowest power consumption and even shuts down the crystal oscillator circuit between cli and clo. therefore, if cli and clo are being used with a crystal to generate the master clock, this circuit is powered down and there is no clock signal. when returning from standby3 mode to normal operation, the timing core must be reset at least 500 s after the standby register is written to. this allows sufficient time for the crystal circuit to settle. the vertical outputs can also be programmed to hold a specific value during the standby3 mode by using address 0x26. this register is useful during power-up if different polarities are required by the v-driver and ccd to prevent damage when vh and vl areas are applied. the polarities for standby1 mode and standby2 mode are also programmable, using address 0x25. outcontrol = low also uses the same polarities programmed for standby1 and standby2 modes in address 0x25. the gpo polarities are programmable using address 0x27. note that the gpo outputs are high-z by default at power-up until address 0x78 is used to select them as outputs. cli frequency change if the input clock cli is interrupted or changed to a different frequency, the timing core must be reset for proper operation. after the cli clock has settled to the new frequency, or the previous frequency is resumed, write 0 and then 1 to the tgcore_rstb register (address 0x14). this guarantees that the timing core operates properly.
ad9927 rev. 0 | page 77 of 100 table 46. standby mode operation (standby polariti es for xv, xsubck, gpo outputs are programmable) i/o block standby3 (default) 1, 2 outcontrol = low 2 standby2 3, 4 standby1 3, 4 afe off no change off only reft, refb on timing core off no change off on clo oscillator off no change off on clo low no change low running h1 high-z low low (4.3 ma) low (4.3 ma) h2 high-z high high (4.3 ma) high (4.3 ma) h3 high-z low low (4.3 ma) low (4.3 ma) h4 high-z high high (4.3 ma) high (4.3 ma) h5 high-z low low (4.3 ma) low (4.3 ma) h6 high-z high high (4.3 ma) high (4.3 ma) h7 high-z low low (4.3 ma) low (4.3 ma) h8 high-z high high (4.3 ma) high (4.3 ma) hl high-z low low (4.3 ma) low (4.3 ma) rg high-z low low (4.3 ma) low (4.3 ma) vd low vdhdpol value vdhdpol value running hd low vdhdpol value vdhdpol value running dclk low running low running dout low low low low xv1 to xv24 low low low low xsubck low low low low gpo1 to gpo8 low low low low 1 to exit standby3, write 00 to standby (address 0x00, bits [1:0]), and then reset the timing core after 500 s to guarantee pro per settling of the oscillator and external crystal. 2 standby3 mode takes priority over outcontrol for determining the output polarities. 3 these polarities assume outcontrol = high because outcontrol = low takes priority over standby1 and standby2. 4 standby1 and standby2 set h and rg dr ive strength to minimum value (4.3 ma).
ad9927 rev. 0 | page 78 of 100 circuit layout information the pcb layout is critical in achieving good image quality from the ad9927. all of the supply pins, particularly the avdd, tcvdd, rgvdd, and hvdd supplies, must be decoupled to ground with good quality high frequency chip capacitors. the decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. if possible, there should be a 4.7 f or larger value bypass capacitor for each main supplyavdd, hvdd, and drvddalthough this is not necessary for each individual pin. in most applications, the supply for rgvdd and hvdd is shared, which can be done as long as the individual supply pins are separately bypassed with 0.1 f capacitors. a separate 3 v supply can also be used for drvdd, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. a separate ground for drvss is not recommended. the analog bypass pins (reft and refb) should be carefully decoupled to ground as close as possible to their respective pins. the analog input (ccdin) capacitor should be located close to the pin. the h1 to h8, hl, and rg traces should be designed to have low inductance to minimize distortion of the signals. the complementary signals, h1/h3/h5/h7 and h2/h4/h6/h8, should be routed as close together and as symmetrically as possible to minimize mutual inductance. heavier pcb traces are recommended because of the large transient current demand on h1 to h8 by the ccd. if possible, physically locating the ad9927 closer to the ccd reduces the inductance on these lines. as always, the routing path should be as direct as possible from the ad9927 to the ccd. note that it is recommended that all h1 to h8 outputs on the ad9927 be used together for maximum flexibility in drive strength settings. a typical ccd with h1 and h2 inputs only should have the ad9927s h1, h3, h5, and h7 outputs connected together to drive the ccds h1, and h2, h4, h6, and h8 outputs connected together to drive the ccds h2. similarly, a ccd with h1, h2, h3, and h4 inputs should have the following: ? h1 and h3 connected to the ccds h1. ? h2 and h4 connected to the ccds h2. ? h5 and h7 connected to the ccds h3. ? h6 and h8 connected to the ccds h4. typical 3 v system the ad9927 typical circuit connections for a 3 v system are shown in figure 94. this application uses an external 3.3 v supply, which is connected to the ad9927s ldo input. the ldo is configured to output 1.8 v for the ad9927s core supply by connecting the ldo1p8en pin to 3.3 v and the ldo3p2en pin to ground. the ldoout and sense pins are shorted together and used to supply 1.8 v to the avdd, tcvdd, and dvdd pins. typical 1.8 v system the internal ldo can be disabled by tying the ldo pins to ground (ldoin, ldo1p8en, ldo3p2en, ldoout, and sense). in this case, an external 1.8 v regulator is required to supply 1.8 v to the avdd, tcvdd, and dvdd pins. all of the ad9927s remaining supplies can be directly supplied with 1.8 v. the internal charge pump (cp) can be used to generate 3.3 v for the h and rg supplies. the ad9927 typical circuit connections for a 1.8 v system are shown in figure 95. external crystal application the ad9927 contains an on-chip oscillator for driving an external crystal. figure 96 shows an example application using a typical 27 mhz crystal. for the exact values of the external resistors and capacitors, it is best to consult the crystal manufacturers data sheet. note that a 2 crystal is not recommended for use with the clo oscillator circuit. the crystal frequency should not exceed 40 mhz.
ad9927 rev. 0 | page 79 of 100 v-driver power supply sequencing when powering up the v-driver of the ad9927, it is important to pay attention to the order that the various v-driver power supplies are turned on. particularly, a bias voltage of 2.3 v or greater must be applied to the v5v pin prior to powering up the vh and vl supplies. v5v is an internal voltage that eventually rises to ~5.4 v after vh and vl are powered up; therefore, it needs to be driven through a diode. a schottky diode is recommended to maximize the bias voltage on v5v. to ensure proper operation, adhere to the following steps: 1. connect vdd1 and vdd2 to a 3 v supply and keep v5v low. 2. perform any necessary writes to registers 0x25 and 0x26 (vt_stby12 and vt_stby3, respectively) to define the polarities of the v-driver outputs prior to powering up the vh and vl supplies. 3. bring the signal driving the diode to v5v high. (note that a gpo output can be used for this operation.) 4. after v5v reaches a minimum of 2.3 v, vh and vl can be powered on. there are no restrictions to the order in which vh and vl can be powered on at this time. 0 5892-001 0v v dd vl v5v v h figure 93. suggested power-up sequence for ad9927 v-driver supplies
ad9927 rev. 0 | page 80 of 100 external r eset in v2a v2b v3a v3b v4 v5 v6 v7 b6 a7 b7 a8 b8 a9 b9 a10 a2 k12 h12 j8 j7 k8 e10 a1 j12 f3 j6 g3 a11 a12 b10 b12 c6 c9 c12 j3 h3 k4 j4 d9 d12 e9 e12 gpo8 gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 rstb sync vd hd iovdd iovss xvvdd xsubcnt v8 v9 v10 v11 v12 v13 v14 v15 dvss (lsb) d0 d1 d2 d3 d4 d5 d6 f11 g11 h11 j11 m11 m10 l9 m12 l10 l11 k9 l12 k10 k11 j10 k6 k7 m9 sck sdata sl refb reft avss ccdin cli clo clivdd tcvss rg rgvss hl d7 d8 d11 d12 d13 (msb) dclk l8 c10 m6 l4 g2 k2 e11 c2 l5 e2 f10 f1 e1 f9 d2 d1 c1 b2 b1 b11 l6 l7 m4 h8 h7 h4 h3 h2 h1 ldoin ldoout sense ldo1p8en ldovss ldo3p2en cpcli cp1p8 cpvss cpfcb cpfct cp3p3 8 general-purpose outputs note: one gpo is needed to drive v5v (pin e10) through diode 18 3 14 d a ta outputs dclk output 0.1f +1.8v ldo out to avdd, tcvdd, dvdd +3v ldo input h1,h2toccd h3,h4toccd +3v cli supply h7, h8 to ccd h5,h6toccd serial interface (from asic/dsp) 0.1f 0.1f analog output from ccd 0.1f rg to ccd hl to ccd ad9927 bbcz not drawn to scale external sync in vertical sync in/out horizontal sync in/out 0.1f +3v supply vll vl1 vl2 vmm vm1 vm2 vh1 vh2 vh supply vl supply vdd2 vdd1 vss2 vss1 v1a v1b subck output (to ccd) subck h4 g 4 vertical output (to ccd) f4 e4 e3 d4 d3 d5 d6 d7 c7 c8 d8 g10 d11 c3 k3 j5 h9 c11 k5 c4 m2 c5 l3 +3v supply test1 test3 v5v h10 xsubcnt input (from gpo or tie to +3v) test4 test5 nc nc nc nc nc nc nc nc nc nc nc h1 l1 1.0f 25v 4.7f 10v 0.1f 10v 0.1f 25v dvdd +1.8v ldo out +3vh,rgsupply avdd tcvdd rgvdd hvdd1 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f 6.3v hvdd2 0.1f hvss2 hvss1 drvss 0.1f drvdd 0.1f j1 h2 g1 f2 m8 m7 m5 m3 m1 l2 master clock input (3v logic) optional clock oscillator output (for crystal application) b4 a4 b3 a3 a6 f12 nc test2 test6 d10 g9 j9 test0 h6 h5 k1 j2 d9 b5 d10 a5 nc g12 +3v supply gpo output (see power-up procedure) 0 5892-101 figure 94. typical 3 v circuit configuration
ad9927 rev. 0 | page 81 of 100 external reset in v2a v2b v3a v3b v4 v5 v6 v7 b6 a7 b7 a8 b8 a9 b9 a10 a2 k12 h12 j8 j7 k8 e10 a1 j12 f3 j6 g3 a11 a12 b10 b12 c6 c9 c12 j3 h3 k4 j4 d9 d12 e9 e12 gpo8 gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 rstb sync vd hd iovdd iovss xvvdd xsubcnt v8 v9 v10 v11 v12 v13 v14 v15 dvss (lsb) d0 d1 d2 d3 d4 d5 d6 f11 g11 h11 j11 m11 m10 l9 m12 l10 l11 k9 l12 k10 k11 j10 k6 k7 m9 sck sdata sl refb reft avss ccdin cli clo tcvss rg rgvss hl d7 d8 d11 d12 d13 (msb) dclk l8 c10 m6 l4 g2 k2 e11 c2 h8 h7 h4 h3 h2 h1 ldovss cpvss 8 general-purpose outputs note: one gpo is needed to drive v5v (pin e10) through diode 18 3 14 data outputs dclk output h1, h2 to ccd h3, h4 to ccd h7, h8 to ccd h5, h6 to ccd serial interface (from asic/dsp) 0.1f 0.1f analog output from ccd 0.1f rg to ccd hl to ccd AD9927BBCZ not drawn to scale external sync in vertical sync in/out horizontal sync in/out 0.1f +3v cp output vll vl1 vl2 vmm vm1 vm2 vh1 vh2 vh supply vl supply vdd2 vdd1 vss2 vss1 v1a v1b subck output (to ccd) subck h4 g 4 vertical output (to ccd) f4 e4 e3 d4 d3 d5 d6 d7 c7 c8 d8 g10 d11 c3 k3 j5 h9 c11 k5 c4 m2 c5 l3 +1.8v supply test1 test3 v5v h10 xsubcnt input (from gpo or tie to +3v) test4 test5 nc nc nc nc nc nc nc nc nc nc nc 1.0f 25v 4.7f 10v 0.1f 10v 0.1f 25v hvss2 hvss1 drvss 0.1f drvdd 0.1f j1 h2 g1 f2 m8 m7 m5 m3 m1 l2 master clock input (3v logic) optional clock oscillator output (for crystal application) b4 a4 b3 a3 a6 f12 nc test2 test6 d10 g9 j9 test0 h6 h5 k1 j2 d9 b5 d10 a5 nc g12 gpo output (see power-up procedure) clivdd l5 e2 f10 f1 e1 f9 d2 d1 c1 b2 b1 b11 l6 l7 m4 ldoin ldoout sense ldo1p8en ldo3p2en cpcli cp1p8 cpfcb cpfct cp3p3 +1.8v cli supply h1 l1 dvdd +1.8v supply +3v cp output avdd tcvdd rgvdd hvdd1 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f 6.3v hvdd2 0.1f +1.8v cp input 0.1f 3.3f +3v cp output 0 5892-102 +3v cp output figure 95. typical 1.8 v circuit configurat ion using charge pump for hvdd and rgvdd 5pf ~ 20pf 5pf ~ 20pf cli clo ad9927 24mhz to 36mhz xtal 2m ? 0 ? ~ 500 ? 375 ? k7 k6 05892-077 figure 96. crystal application using cli/clo (consult crystal data sheet for component values)
ad9927 rev. 0 | page 82 of 100 serial interface timing the internal registers of the ad9927 are accessed through a 3-wire serial interface. each register consists of a 12-bit address and a 28-bit data-word. both the 12-bit address and 28-bit data- word are written starting with the lsb. to write to each register, a 40-bit operation is required, as shown in figure 97. although many registers are fewer than 28 bits wide, all 28 bits must be written for each register. for example, if the register is only 20 bits wide, the upper eight bits are dont cares and must be filled with 0s during the serial write operation. if fewer than 28 data bits are written, the register is not updated with new data. figure 98 shows a more efficient way to write to the registers, using the ad9927s address autoincrement capability. using this method, the lowest desired address is written first, followed by multiple 28-bit data-words. each new 28-bit data-word is automatically written to the next highest register address. by eliminating the need to write each 12-bit address, faster register loading is achieved. continuous write operations can be used starting with any register location. a4 a5 a2 a3 sdata a0 a1 a6 a8 a9 a10 a11 d0 d1 d2 d3 d25 d26 d27 sl a7 t ls t ds 12-bit a dd r ess 28-bit data 5 40 6 7 8 9 10 11 12 13 14 15 16 38 39 t lh t dh sck 1234 notes 1. sdata bits are latched on sck rising edges. sck can idle high or low between write operations. 2. all 40 bits must be written: 12 bits for address and 28 bits for data. 3. if the register length is <28 bits, 0s must be used to complete the 28-bit data length. 4. new data values are updated in the specified register location at different times, depending on the particular register written to. see the updating of new register values section for more information. 0 5892-078 figure 97. serial write operation s data a0 a1 a2 a10 a11 d0 d1 d26 d27 sck sl a3 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest) register address is written, followed by multiple 28-bit data-words. 3. the address automatically increments with each 28-bit data-word (all 28 bits must be written). 4. sl is held low until the last desired register has been loaded. d0 d1 d26 d27 d0 data for starting register address data for next register address d2 d1 1 40 234 11121314 39 42 41 68 67 70 69 71 0 5892-079 figure 98. continuous serial write operation
ad9927 rev. 0 | page 83 of 100 layout of internal registers the ad9927 address space is divided into two register areas, as illustrated in figure 99. in the first address space, address 0x00 to address 0xff contain the registers for the afe, miscellaneous, vd/hd, i/o and cp, timing core, shutter and gpo, and update control functions. the second address space, beginning at address 0x800, consists of the v-pattern groups, v-sequences, and field registers. this is a configurable set of registers; the user can decide how many v-pattern groups, v-sequences, and fields are used in a particular design. therefore, the addresses for these registers vary, depending on the number of v-patterns and v-sequences chosen. address 0x28 specifies the total number of v-pattern groups and v-sequences used. the starting address for the v-pattern groups is always 0x800. the starting address for the v-sequences is based on the number of v-pattern groups used, with each v-pattern group occupying 48 register addresses. the starting address for the field registers depends on both the number of v-pattern groups and the number of v-sequences. each v-sequence occupies 40 register addresses, and each field occupies 16 register addresses. the starting address for the v-sequences is equal to 0x800 plus the number of v-pattern groups times 48. the starting address for the fields is equal to the starting address of the v-sequences plus the number of v-sequences times 40. the v-pattern, v-sequence, and field registers must always occupy a continuous block of addresses. figure 100 shows an example in which three v-pattern groups, four v-sequences, and two fields are used. the starting address for the v-pattern groups is always 0x800. since vpatnum = 3, the v-pattern groups occupies 144 address locations. the start of the v-sequence registers is 0x890 (that is, 0x800 + 144). with vseqnum = 4, the v-sequences occupy 160 address locations. therefore, the field registers begin at 0x930 (that is, 0x890 + 160). the ad9927 address space contains many unused addresses. undefined addresses between address 0x00 and address 0xff should not be written to; otherwise, the ad9927 may operate incorrectly. continuous register writes should be performed carefully so that undefined registers are not written to. fixed register ar e a addr 0x00 v-pattern groups v-sequences configurable registe r a r ea vpat start 0x800 fields max 0xfff vseq start field start addr 0xff afe registers update control registers miscellaneous registers vd/hd registers i/o and cp registers test registers timing core registers mode registers test registers shutter and gpo registers invalid do not access 05892-080 figure 99. layout of ad9927 registers a dd r 0x800 a dd r 0x890 a dd r 0x930 a dd r 0x950 max 0xfff 3 v-pattern groups (483=144registers) 4 v-sequences (404=160registers) 2fields (162=32registers) unused memory 05892-081 figure 100. example re gister configuration
ad9927 rev. 0 | page 84 of 100 updating new register values the ad9927s internal registers are updated at different times, depending on the particular register. table 47 summarizes the four register update types: sck, vd, sg-line, and scp. tables in the complete register listing section also contain an update type column that identifies when each register is updated. ? sck updated as soon as the 28th data bit (d27) is clocked in, some registers are immediately updated. these registers are used for functions that do not require gating with the next vd boundary, such as power-up and reset functions. ? vd updated more registers are updated at the next vd falling edge. by updating these values at the next vd edge, the current field is not corrupted and the new register values are applied to the next field. the vd update can be further delayed past the vd falling edge by using the update register (address 0x17). this delays the vd-updated register updates to any hd line in the field. note that the field registers are not affected by the update register. ? sg-line updated a few of the shutter registers are updated at the hd falling edge at the start of the sg active line. these registers control the subck signal so that the subck output is not updated until the sg line occurs. ? scp updated at the next scp where they are used, the v-pattern group and v-sequence registers are updated. for example, in figure 101 this field has selected region 1 to use vseq3 for the vertical outputs. this means that a write to any of the vseq3 registers, or any of the v-pattern group registers, which are referenced by vseq3, updates at scp1. if multiple writes are done to the same register, the last one done before scp1 is the one that is updated. likewise, register writes to any vseq5 registers are updated at scp2, and register writes to any vseq8 registers are updated at scp3. caution it is recommended that the registers in the configurable address area not be written within 36 pixels of any hd falling edge where a sequence change position (scp) occurs. see figure 91 and figure 92 for an example of what this inhibit area looks like in master and slave modes. this restriction applies to the v- pattern, v-sequence, and field registers. as shown in figure 101, writing to these registers before the vd falling edge typically avoids loading these registers during scp locations. table 47. register update locations update type description sck when the 28th data bit (d27) is clocke d in, the register is immediately updated. vd register is updated at the vd falling edge. vd-updated regist ers can be delayed further by using the update register at address 0x17. field registers are not affected by the update register. sg-line register is updated at the hd fallin g edge at the start of the sg-active line. scp register is updated at the next scp when the register is used. vd region 0 hd scp1 scp2 scp3 region 1 region 2 region 3 vsg sgline scp0 serial write sck updated scp0 v d updated s g updated scp updated xv1 to xv24 use vseq2 use vseq3 use vseq5 use vseq8 05892-082 figure 101. register update locations (see table 47 for definitions)
ad9927 rev. 0 | page 85 of 100 complete register listing when an address contains less than 28 data bits, all remaining bits must be written as 0s. table 48. afe registers address data bits default value update type name description 00 [1:0] 3 sck standby standby modes. 0: normal operation; 1: standby1 mode; 2: standby2 mode; 3: standby3 mode. [2] 1 clpenable 0: disable ob clamp; 1: enable ob clamp. [3] 0 clpspeed 0: select normal ob clamp settling; 1: select fast ob clamp settling. [4] 0 fastupdate 0: ignore cds gain; 1: ve ry fast clamping when cds gain is updated. [5] 0 pblk_lvl 0: blank data outputs to 0 during pblk; 1: blank data outputs to programmed clamp level during pblk. [6] 0 dcbyp 0: enable input dc restore circuit during pblk; 1: disable input dc restore circuit during pblk. 01 [0] 0 sck doutdisable 0: data outputs are driven; 1: data outputs are three-stated. [1] 0 doutlatch 0: latch data outputs using the rising edge of doutphasep (doutphasep register setting); 1: output latch is transparent. [2] 0 gray_en 1: enable gray enco ding of the digital data outputs. [3] 1 test set to 0. 02 [0] 0 sck test do not access, or set to 0. 03 [23:0] ffffff sck test do not access, or set to 0xffffff. 04 [2:0] 0 vd cdsgain cds gain setting. 0: ?3 db; 4: 0 db; 6: +3 db; 7: +6 db. all other values are invalid. 05 [9:0] f vd vgagain vga gain, 6 db to 42 db (0.035 db per step). 06 [9:0] 1ec vd clamplevel optical black clamp level, 0 to 1023 lsb (1 lsb per step). 0d [0] 0 vd clidivide 0: no division of cli; 1: divide cli input frequency by 2. table 49. miscellaneous registers address data bits default value update type name description 10 [0] 0 sck sw_rst software reset. bit self-clears to 0 when a reset occurs. 1: reset address 0x00 to addr ess 0xff to default values. 11 [0] 0 vd outcontrol 0: make all outputs dc inactive; 1: enable outputs at next vd edge. 12 [0] 0 sck rstb_en 1: configure sync pin as rstb input signal. [4:1] 0 test test mode only. must be set to 0. 13 [0] 1 sck syncenable 1: external synchronization enable (configures pin d3 as an input). [1] 0 syncpol sync active polarity. [2] 0 syncsuspend suspend clocks during sync active pulse. 0: dont suspend; 1: suspend. [3] 0 enh_sync_en 1: enable enhanced sync/shutter operations. [4] 0 sync_mask_hd 1: mask hd during syncsuspend. [5] 1 sync_mask_vd 1: mask vd during syncsuspend. [6] 1 sync_mask_v 1: mask xv outputs during syncsuspend. [7] 0 shadow_en 1: enable use of shadow registers. [12:8] 0 test test mode only. must be set to 0. [13] 0 update_shadow 1: writes to shadow bits affect shadow registers, not primary. [14] 0 swsync 1: initiate software sync event (self-clears to 0 after sync). 14 [0] 0 sck tgcore_rstb timing core reset bar. 0: reset tg core; 1: resume operation.
ad9927 rev. 0 | page 86 of 100 address data bits default value update type name description 15 [0] 0 sck osc_rstb clo oscillator reset bar. 0: oscillator in power-down state; 1: resume oscillator operation. 16 [27:0] 0 sck test test mode only. must be set to 0. 17 [12:0] 0 sck update serial update line. sets the line (hd) within the field to update the vd-updated registers. [13] 0 preventup prevents the update of the vd-updated registers. 0: normal update; 1: prevent update of vd-updated registers. [14] 0 sync_rst_shuten 1: enable reset of the shutter control after sync operation occurs. [15] 0 reg_rst_shut 1: forces shutter control to reset. [16] 0 gpo_rst_sync 1: reset shutter and gpo control at sync operation. 18 [27:0] 0 sck test test mode only. must be set to 0. 19 [27:0] 0 sck test test mode only. must be set to 0. 1a [27:0] 0 sck test test mode only. must be set to 0. 1b [27:0] a sck test test mode only. must be set to 0xa. 1c [23:0] ff0000 sck vsgselect each bit selects xv pulses for use as vsg pulses. 1d [23:0] 0 sck vsgmask_ctl vsg masking. overrides settings in field registers when enabled. [24] 0 vsgmask_ctl_en 0: disable vsgmak_ctl bits. vsg masking is controlled by field registers. 1: enable vsgmask_ctl bits to control vsg masking 1f [0] 1 sck hcnt14_en 1: enable 14-bit h-counter. [1] 1 pblk_mask_en 1: disable clamp operation if pblk is active at the same time as clpob. table 50. vd/hd registers address data bits default value update type name description 20 [0] 0 sck master vd/hd master or slave mode. 0: slave mode; 1: master mode. 21 [0] 0 vd vdhdpol vd/hd active polarity. 0 = low, 1 = high. 22 [12:0] 0 vd hdrise rising edge location for hd. minimum value is 36 pixels. [25:13] 0 vdrise rising edge location for vd. table 51. i/o and charge pump registers address data bits default value update type name description 23 [0] 0 sck osc_nvr oscillator normal voltage range. se t to match clivdd supply voltage. 0 = 1.8 v, 1 = 3.3 v [1] 0 xv_nvr xv output normal voltage range. set to match xvvdd supply voltage. 0 = 1.8 v, 1 = 3.3 v [2] 0 io_nvr i/o normal voltage range. set the match iovdd supply voltage. 0 = 1.8 v, 1 = 3.3 v [3] 0 data_nvr data pin normal voltage range. set to match drvdd supply voltage. 0 = 1.8 v i/o, 1 = 3.3 v i/o. [4] 0 test test use only. set to 0. [5] 0 test test use only. set to 0. [6] 0 ldo_32_en 1: internal regulator enable for 3.2 v output. [9:7] 1 hclkmode selects hclk output configuration. should be written to desired value. 001 = mode 1, 010 = mode 2, 100 = mode 3. all other values are invalid.
ad9927 rev. 0 | page 87 of 100 address data bits default value update type name description 24 [0] 0 sck sel_vco 1: internal cp clock select vco. [1] 1 sel_div 1: internal cp clock select divided-down version of cli (default). [2] 0 sel_cli 1: internal cp clock select cli. [3] 0 o31v 1: cp output voltage is 3.1 v. [4] 0 o32v 1: cp output voltage is 3.2 v. [5] 1 o33v 1: cp output voltage is 3.3 v. [6] 0 o34v 1: cp output voltage is 3.4 v. [7] 1 test test use only. use default values only. [8] 1 test test use only. use default values only. [9] 1 test test use only. use default values only. [10] 1 test test use only. use default values only. [11] 0 test test use only. use default values only. [12] 0 test test use only. use default values only. [13] 0 test test use only. use default values only. [14] 1 cp_pdn charge pump power-down. 1: power-down; 0: cp is running. 25 [24:0] 0 sck vt_stby12 [23:0] standby1 and standby2 polarity for xv[23:0]. [24] standby1 and standby2 polarity for xsubck. settings also apply when outcontrol = low. 26 [24:0] 0 sck vt_stby3 [23:0] standby3 polarity for xv [23:0]. [24] standby3 polarity for xsubck. 27 [7:0] 0 sck gp_stdby12 standby1 and standby2 polarity for gpo [7:0]. settings also apply when outcontrol = low. [15:8] gp_stdby3 standby3 polarity for gpo [7:0]. table 52. memory configuration and mode registers address data bits default value update type name description 28 [4:0] 0 sck vpatnum total number of v-pattern groups. [9:5] 0 seqnum total number of v-sequences. 2a [2:0] 0 sck mode total number of fields in mode. 2b [4:0] 0 sck field0 selected first field in mode. [9:5] 0 field1 selected second field in mode. [14:10] 0 field2 selected third field in mode. [19:15] 0 field3 selected fourth field in mode. [24:20] 0 field4 selected fifth field in mode. 2c [4:0] 0 sck field5 selected sixth field in mode. [9:5] 0 field6 selected seventh field in mode. table 53. timing core registers address data bits default value update type name description 30 [5:0] 0 sck h1posloc h1 rising edge location. [13:8] 20 h1negloc h1 falling edge location. [16] 1 h1pol h1 polarity control. 0: inverse of figure 20; 1: no inversion. 31 [5:0] 0 sck h2posloc h2 rising edge location (h5 in hclk mode 3). [13:8] 20 h2negloc h2 falling edge location (h5 in hclk mode 3). [16] 1 h2pol h2 polarity (h5 in hclk mode 3). 0: inverse of figure 20; 1: no inversion. 32 [5:0] 0 sck hlposloc hl rising edge location. [13:8] 20 hlnegloc hl falling edge location. [16] 1 hlpol hl polarity control. 0: inverse of figure 20; 1: no inversion.
ad9927 rev. 0 | page 88 of 100 address data bits default value update type name description 33 [5:0] 0 sck rgposloc rg rising edge location. [13:8] 10 rgnegloc rg falling edge location. [16] 1 rgh2pol rg polarity control. 0: inverse of figure 20, 1: no inversion. 34 [0] 0 sck h1hblkretime retime h1, h2, hl hblk to the internal clock. 0: no retime; 1: retime. [1] 0 h2hblkretime recommended setting is retime enabled (1). setting to 1 adds one cycle delay to programmed hblk positions. [2] 0 hlhblkretime [3] 0 hl_hblk_en enable hblk for hl output. 0: disable; 1: enable. [7:4] 4 hclk_width enables wide h-clocks during hblk interval. set to 0 to disable. 35 [2:0] 1 sck h1drv h1 drive strength. 0: off; 1: 4.3 ma; 2: 8.6 ma; 3: 12.9 ma; 4: 4.3 ma; 5: 8.6 ma; 6: 12.9 ma; 7: 17.2 ma. [6:4] 1 h2drv h2 drive strength (same range as h1drv). [10:8] 1 h3drv h3 drive strength (same range as h1drv). [14:12] 1 h4drv h4 drive strength (same range as h1drv). [18:16] 1 hldrv hl drive strength (same range as h1drv). [22:20] 1 rgdrv rg drive strength (same range as h1drv). 36 [2:0] 1 sck h5drv h5 drive strength (same range as h1drv). [6:4] 1 h6drv h6 drive strength (same range as h1drv). [10:8] 1 h7drv h7 drive strength (same range as h1drv). [14:12] 1 h8drv h8 drive strength (same range as h1drv). 37 [5:0] 0 sck shdloc shd sampling edge location. [11:6] 20 shploc shp sampling edge location. [17:12] 10 shpwidth shp width (controls input dc restore switch active time). 38 [5:0] 0 sck doutphasep dout phase control, positive edge. specifies location of dout. [11:6] 20 doutphasen dout phase control, negative edge. always set to doutphasep plus 32 edges to maintain 50% duty cycle of internal doutphase clocking. [12] 0 dclkmode dclk mode. 0: dclk tracks dout; 1: dclk phase is fixed. [14:13] 0 doutdelay data output delay (t od ) with respect to dclk rising edge. 0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns [15] 0 dclkinv invert dclk output. 0: no inversion, 1: inversion of dclk. 39 [2:0] 7 sck cphmask enable h-masking during cp operation. table 54. test registersdo not access address data bits default value update name description 3e ~ 4f test registers only. do not access. table 55. test registersdo not access address data bits default value update type name description 50 ~ 6f test registers only. do not access. table 56. shutter and gpo registers address data bits default value update type name description 70 [2:0] 0 vd primary_action selects action for primary and secondary counters. [5:3] 0 second_action 0: idle (do nothing) autoreset on vd. 1: activate counter (primary: auto exposure/readout). 2: rapidshot: wrap/repeat counter. 3: shottimer: delay start of count. 4: shottimer with rapidshot. 5: slr exposure (manual).
ad9927 rev. 0 | page 89 of 100 address data bits default value update type name description 6: slr read (manual). 7: force to idle. [13:6] 0 manual_trig 1: manual trigger for gp signals, when protocol 1 is selected. bit [6] : gp1 manual trigger bit [13] : gp8 manual trigger 71 [12:0] 0 vd primary_max primary counter maximum value. [24:13] 0 second_max secondary counter maximum value. [27:25] 0 vdhd_mask mask vd/hd during counter operation. 72 [12:0] 0 vd primary_delay number of fields to delay before the next count (exposure) starts. shottimer with rapidshot, skip delay before first count (exposure). [13] 0 primary_skip number of fields to delay before the next count starts. shottimer with rapidshot, skip delay before first count. [26:14] 0 second_delay [27] 0 second_skip 73 [2:0] 0 vd gp1_protocol selects protocol for each general-purpose signal. [5:3] 0 gp2_protocol idle = 0. [8:6] 0 gp3_protocol no counter association = 1. [11:9] 0 gp4_protocol link to primary = 2. [14:12] 0 gp5_protocol link to secondary = 3. [17:15] 0 gp6_protocol link to mode = 4. [20:18] 0 gp7_protocol primary repeat = 5. [23:21] 0 gp8_protocol secondary repeat = 6. keep on = 7. 74 [12:0] 0 vd sgmask_num exposure: number of fields to mask sgs. [25:13] 0 subckmask_num exposure plus read out: number of fields to mask subck. [26] 1 subcktog_update 0: subck toggles (register 0x77) updated on sg line. 1: subck toggles (register 0x77) updated on update line (vd-updated) [27] 0 subckmask_skip1 skip the subck mask for the first exposure field only. typically set to 1. 75 [0] 0 sg test reserved for test purpose. must be set to 0. [13:1] 0 subckstartline line location after vsg line to begin subck pulses. must not be set to 1. [26:14] 0 subcknum number of subck pulses per field. must be set less than vdlen. [27] 0 sg_suppress suppress the sg and allow subck to finish at subcknum. 76 [12:0] 1fff vd subck_tog1 subck toggle position 1. [25:13] 1fff subck_tog2 subck toggle position 2. [26] 0 subck_pol subck start polarity. 77 [12:0] 1fff vd/sg subckhp_tog1 hi-precision subck toggle position 1. [25:13] 1fff subckhp_tog2 hi-precision subck toggle position 2. 78 [0] 0 vd gp1_pol gp1 low/high start polarity. [1] 0 gp2_pol gp2 low/high start polarity. [2] 0 gp3_pol gp3 low/high start polarity. [3] 0 gp4_pol gp4 low/high start polarity. [4] 0 gp5_pol gp5 low/high start polarity. [5] 0 gp6_pol gp6 low/high start polarity. [6] 0 gp7_pol gp7 low/high start polarity. [7] 0 gp8_pol gp8 low/high start polarity. [8] 1 sel_gp1 1 = gp1 signal is selected for gpo1 output. [9] 1 sel_gp2 1 = gp2 signal is selected for gpo2 output. [10] 1 sel_gp3 1 = gp3 signal is selected for gpo3 output. [11] 1 sel_gp4 1 = gp4 signal is selected for gpo4 output. 0 = subck is selected. [12] 1 sel_gp5 1 = gp5 signal is selected for gpo5 output. 0 = xv21 is selected.
ad9927 rev. 0 | page 90 of 100 address data bits default value update type name description [13] 1 sel_gp6 1 = gp6 signal is selected for gpo6 output. 0 = xv22 is selected. [14] 1 sel_gp7 1 = gp7 signal is selected for gpo7 output. 0 = xv23 is selected. [15] 1 sel_gp8 1 = gp8 signal is selected for gpo8 output. 0 = xv24 is selected. [23:16] 0 gpo_output_en 1 = gpo outputs enable d. 0 = gpo is input high-z state (default). [24] 0 gpo5_override 1 = when gpo5 config ured as input, overri des internal out_cont. [25] 0 gpo6_override 1 = when gpo6 conf igured as input, ove rrides internal hblk. [26] 0 gpo7_override 1 = when gpo7 config ured as input, overri des internal clpob. [27] 0 gpo8_override 1 = when gpo8 conf igured as input, ove rrides internal pblk. 79 [7:0] 0 vd gp[*]_use_lut use result from lut, or else gp* is unaltered. [11:8] {0, 0, 0, 0} lut_for_gp12 two-input look-up table results. [15:12] {0, 0, 0, 0} lut_for_gp34 examples: {lut_for_gp12} ? [gp2:gp1]. [19:16] {0, 0, 0, 0} lut_for_gp56 {0, 1, 1, 0} = gp2 xor gp1; {1, 1, 1, 0} = gp2 or gp1. [23:20] {0, 0, 0, 0} lut_for_gp78 {0, 1, 1, 1} = gp2 nand gp1; {1, 0, 0, 0} = gp2 and gp1. 7a [12:0] 0 vd gp1_tog1_fd general-purpose signal 1, first toggle position, field location. [25:13] 0 gp1_tog1_ln general-purpose sign al 1, first toggle position, line location. 7b [12:0] 0 vd gp1_tog1_px general-purpose signal 1, first toggle position, pixel location. [25:13] 0 gp1_tog2_fd general-purpose signal 1, second toggle position, field location. 7c [12:0] 0 vd gp1_tog2_ln general-purpose si gnal 1, second toggle position, line location. [25:13] 0 gp1_tog2_px general-purpose signal 1, second toggle position, pixel location. 7d [12:0] 0 vd gp1_tog3_fd general-purpose si gnal 1, third toggle position, field location. [25:13] 0 gp1_tog3_ln general-purpose sign al 1, third toggle position, line location. 7e [12:0] 0 vd gp1_tog3_px general-purpose signal 1, third toggle position, pixel location. [25:13] 0 gp1_tog4_fd general-purpose signal 1, fourth toggle posit ion, field location. 7f [12:0] 0 vd gp1_tog4_ln general-purpose si gnal 1, fourth toggle position, line location. [25:13] 0 gp1_tog4_px general-purpose signal 1, fourth toggle position, pixel location. 80 [12:0] 0 vd gp2_tog1_fd general-purpose si gnal 2, first toggle position, field location. [25:13] 0 gp2_tog1_ln general-purpose sign al 2, first toggle position, line location. 81 [12:0] 0 vd gp2_tog1_px general-purpose si gnal 2, first toggle position, pixel location. [25:13] 0 gp2_tog2_fd general-purpose signal 2, second toggle position, field location. 82 [12:0] 0 vd gp2_tog2_ln general-purpose sign al 2, second toggle position, line location. [25:13] 0 gp2_tog2_px general-purpose signal 2, second toggle position, pixel location. 83 [12:0] 0 vd gp2_tog3_fd general-purpose si gnal 2, third toggle position, field location. [25:13] 0 gp2_tog3_ln general-purpose sign al 2, third toggle position, line location. 84 [12:0] 0 vd gp2_tog3_px general-purpose si gnal 2, third toggle position, pixel location. [25:13] 0 gp2_tog4_fd general-purpose signal 2, fourth toggle posit ion, field location. 85 [12:0] 0 vd gp2_tog4_ln general-purpose sign al 2, fourth toggle position, line location. [25:13] 0 gp2_tog4_px general-purpose signal 2, fourth toggle position, pixel location. 86 [12:0] 0 vd gp3_tog1_fd general-purpose si gnal 3, first toggle position, field location. [25:13] 0 gp3_tog1_ln general-purpose sign al 3, first toggle position, line location. 87 [12:0] 0 vd gp3_tog1_px general-purpose si gnal 3, first toggle position, pixel location. [25:13] 0 gp3_tog2_fd general-purpose signal 3, second toggle position, field location. 88 [12:0] 0 vd gp3_tog2_ln general-purpose sign al 3, second toggle position, line location. [25:13] 0 gp3_tog2_px general-purpose signal 3, second toggle position, pixel location. 89 [12:0] 0 vd gp3_tog3_fd general-purpose si gnal 3, third toggle position, field location. [25:13] 0 gp3_tog3_ln general-purpose sign al 3, third toggle position, line location. 8a [12:0] 0 vd gp3_tog3_px general-purpose signal 3, third toggle position, pixel location. [25:13] 0 gp3_tog4_fd general-purpose signal 3, fourth toggle posit ion, field location. 8b [12:0] 0 vd gp3_tog4_ln general-purpose si gnal 4, fourth toggle position, line location. [25:13] 0 gp3_tog4_px general-purpose signal 4, fourth toggle position, pixel location. 8c [12:0] 0 vd gp4_tog1_fd general-purpose signal 4, first toggle position, field location. [25:13] 0 gp4_tog1_ln general-purpose sign al 4, first toggle position, line location.
ad9927 rev. 0 | page 91 of 100 address data bits default value update type name description 8d [12:0] 0 vd gp4_tog1_px general-purpose signal 4, first toggle position, pixel location. [25:13] 0 gp4_tog2_fd general-purpose signal 4, second toggle position, field location. 8e [12:0] 0 vd gp4_tog2_ln general-purpose si gnal 4, second toggle position, line location. [25:13] 0 gp4_tog2_px general-purpose signal 4, second toggle position, pixel location. 8f [12:0] 0 vd gp4_tog3_fd general-purpose si gnal 4, third toggle position, field location. [25:13] 0 gp4_tog3_ln general-purpose sign al 4, third toggle position, line location. 90 [12:0] 0 vd gp4_tog3_px general-purpose si gnal 4, third toggle position, pixel location. [25:13] 0 gp4_tog4_fd general-purpose signal 4, fourth toggle posit ion, field location. 91 [12:0] 0 vd gp4_tog4_ln general-purpose sign al 4, fourth toggle position, line location. [25:13] 0 gp4_tog4_px general-purpose signal 4, fourth toggle position, pixel location. 92 [12:0] 0 vd gp5_tog1_fd general-purpose si gnal 5, first toggle position, field location. [25:13] 0 gp5_tog1_ln general-purpose sign al 5, first toggle position, line location. 93 [12:0] 0 vd gp5_tog1_px general-purpose si gnal 5, first toggle position, pixel location. [25:13] 0 gp5_tog2_fd general-purpose signal 5, second toggle position, field location. 94 [12:0] 0 vd gp5_tog2_ln general-purpose sign al 5, second toggle position, line location. [25:13] 0 gp5_tog2_px general-purpose signal 5, second toggle position, pixel location. 95 [12:0] 0 vd gp5_tog3_fd general-purpose si gnal 5, third toggle position, field location. [25:13] 0 gp5_tog3_ln general-purpose sign al 5, third toggle position, line location. 96 [12:0] 0 vd gp5_tog3_px general-purpose si gnal 5, third toggle position, pixel location. [25:13] 0 gp5_tog4_fd general-purpose signal 5, fourth toggle posit ion, field location. 97 [12:0] 0 vd gp5_tog4_ln general-purpose sign al 5, fourth toggle position, line location. [25:13] 0 gp5_tog4_px general-purpose signal 5, fourth toggle position, pixel location. 98 [12:0] 0 vd gp6_tog1_fd general-purpose si gnal 6, first toggle position, field location. [25:13] 0 gp6_tog1_ln general-purpose sign al 6, first toggle position, line location. 99 [12:0] 0 vd gp6_tog1_px general-purpose si gnal 6, first toggle position, pixel location. [25:13] 0 gp6_tog2_fd general-purpose signal 6, second toggle position, field location. 9a [12:0] 0 vd gp6_tog2_ln general-purpose si gnal 6, second toggle position, line location. [25:13] 0 gp6_tog2_px general-purpose signal 6, second toggle position, pixel location. 9b [12:0] 0 vd gp6_tog3_fd general-purpose si gnal 6, third toggle position, field location. [25:13] 0 gp6_tog3_ln general-purpose sign al 6, third toggle position, line location. 9c [12:0] 0 vd gp6_tog3_px general-purpose si gnal 6, third toggle position, pixel location. [25:13] 0 gp6_tog4_fd general-purpose signal 6, fourth toggle posit ion, field location. 9d [12:0] 0 vd gp6_tog4_ln general-purpose si gnal 6, fourth toggle position, line location. [25:13] 0 gp6_tog4_px general-purpose signal 6, fourth toggle position, pixel location. 9e [12:0] 0 vd gp7_tog1_fd general-purpose si gnal 7, first toggle position, field location. [25:13] 0 gp7_tog1_ln general-purpose sign al 7, first toggle position, line location. 9f [12:0] 0 vd gp7_tog1_px general-purpose si gnal 7, first toggle position, pixel location. [25:13] 0 gp7_tog2_fd general-purpose signal 7, second toggle position, field location. a0 [12:0] 0 vd gp7_tog2_ln general-purpose si gnal 7, second toggle position, line location. [25:13] 0 gp7_tog2_px general-purpose signal 7, second toggle position, pixel location. a1 [12:0] 0 vd gp7_tog3_fd general-purpose si gnal 7, third toggle position, field location. [25:13] 0 gp7_tog3_ln general-purpose sign al 7, third toggle position, line location. a2 [12:0] 0 vd gp7_tog3_px general-purpose si gnal 7, third toggle position, pixel location. [25:13] 0 gp7_tog4_fd general-purpose signal 7, fourth toggle posit ion, field location. a3 [12:0] 0 vd gp7_tog4_ln general-purpose si gnal 7, fourth toggle position, line location. [25:13] 0 gp7_tog4_px general-purpose signal 7, fourth toggle position, pixel location. a4 [12:0] 0 vd gp8_tog1_fd general-purpose si gnal 8, first toggle position, field location. [25:13] 0 gp8_tog1_ln general-purpose sign al 8, first toggle position, line location. a5 [12:0] 0 vd gp8_tog1_px general-purpose si gnal 8, first toggle position, pixel location. [25:13] 0 gp8_tog2_fd general-purpose signal 8, second toggle position, field location.
ad9927 rev. 0 | page 92 of 100 address data bits default value update type name description a6 [12:0] 0 vd gp8_tog2_ln general-purpose si gnal 8, second toggle position, line location. [25:13] 0 gp8_tog2_px general-purpose signal 8, second toggle position, pixel location. a7 [12:0] 0 vd gp8_tog3_fd general-purpose si gnal 8, third toggle position, field location. [25:13] 0 gp8_tog3_ln general-purpose sign al 8, third toggle position, line location. a8 [12:0] 0 vd gp8_tog3_px general-purpose si gnal 8, third toggle position, pixel location. [25:13] 0 gp8_tog4_fd general-purpose signal 8, fourth toggle posit ion, field location. a9 [12:0] 0 vd gp8_tog4_ln general-purpose si gnal 8, fourth toggle position, line location. [25:13] 0 gp8_tog4_px general-purpose signal 8, fourth toggle position, pixel location. aa [0] 0 vd subck_tog1_13 bit [13] for subck toggle position 1. for 14-bit h-counter mode. [1] 0 vd subck_tog2_13 bit [13] for subck toggle position 2. for 14-bit h-counter mode. [2] 0 vd/sg subckhp_tog1_13 bit [13] for subck hp toggle 1. for 14-bit h-counter mode. [3] 0 vd/sg subckhp_tog2_13 bit [13] for subck hp toggle 2. for 14-bit h-counter mode. table 57. update control registers address data bits default value update name description b0 [15:0] 1803 sck afe_updt_sck each bit corresponds to one address location. afe_updt_sck [0] = 1, update address 0x00 on sl rising edge. afe_updt_sck [1] = 1, update address 0x01 on sl rising edge. afe_updt_sck [15] = 1, update address 0x0f on sl rising edge. b1 [15:0] e7fc sck afe_updt_vd each bit corresponds to one address location. afe_updt_vd [0] = 1, update address 0x00 on vd rising edge. afe_updt_vd [1] = 1, update address 0x01 on vd rising edge. afe_updt_vd [15] = 1, update address 0x0f on vd rising edge. b2 [15:0] f8fd sck misc_updt_sck enable sck update of miscellaneous registers, address 0x10 to address 0x1f. b3 [15:0] 0702 sck misc_updt_vd enable vd update of miscellaneous registers, address 0x10 to address 0x1f. b4 [15:0] fff9 sck vdhd_updt_sck enable sck update of vdhd registers, address 0x20 to address 0x2f. b5 [15:0] 0006 sck vdhd_updt_vd enable vd update of vdhd registers, address 0x20 to address 0x2f. table 58. extra registers address data bits default value update name description d4 [0] 0 sck test test use only. set to 0. [1] 0 gpo_int_en allow observation of internal signals at gpo5 to gpo8 outputs. gpo5: outcontrol. gpo6: hblk. gpo7: clpob. gpo8: pblk. [9:2] 0 test test use only. set to 0. d7 [0] 0 sck test test use only. set to 0. [1] 0 xv24_swap set to 1 to change the v-driver o utput configuration so that xv15 is output on the xv24 output pin. useful with special vertical sequence alternation mode when the xv24 register is reserved for pattern selection. d8 [27:0] 0 sck start recommended start-up register. should be set to 0x888.
ad9927 rev. 0 | page 93 of 100 table 59. v-pattern group (vpat) register map address data bits default value update type name description 00 [12:0] x scp xv1tog1 xv1 toggle position 1. [25:13] x xv1tog2 xv1 toggle position 2. 01 [12:0] x scp xv1tog3 xv1 toggle position 3. [25:13] x xv1tog4 xv1 toggle position 4. 02 [12:0] x scp xv2tog1 xv2 toggle position 1. [25:13] x xv2tog2 xv2 toggle position 2. 03 [12:0] x scp xv2tog3 xv2 toggle position 3. [25:13] x xv2tog4 xv2 toggle position 4. 04 [12:0] x scp xv3tog1 xv3 toggle position 1. [25:13] x xv3tog2 xv3 toggle position 2. 05 [12:0] x scp xv3tog3 xv3 toggle position 3. [25:13] x xv3tog4 xv3 toggle position 4. 06 [12:0] x scp xv4tog1 xv4 toggle position 1. [25:13] x xv4tog2 xv4 toggle position 2. 07 [12:0] x scp xv4tog3 xv4 toggle position 3. [25:13] x xv4tog4 xv4 toggle position 4. 08 [12:0] x scp xv5tog1 xv5 toggle position 1. [25:13] x xv5tog2 xv5 toggle position 2. 09 [12:0] x scp xv5tog3 xv5 toggle position 3. [25:13] x xv5tog4 xv5 toggle position 4. 0a [12:0] x scp xv6tog1 xv6 toggle position 1. [25:13] x xv6tog2 xv6 toggle position 2. 0b [12:0] x scp xv6tog3 xv6 toggle position 3. [25:13] x xv6tog4 xv6 toggle position 4. 0c [12:0] x scp xv7tog1 xv7 toggle position 1. [25:13] x xv7tog2 xv7 toggle position 2. 0d [12:0] x scp xv7tog3 xv7 toggle position 3. [25:13] x xv7tog4 xv7 toggle position 4. 0e [12:0] x scp xv8tog1 xv8 toggle position 1. [25:13] x xv8tog2 xv8 toggle position 2. 0f [12:0] x scp xv8tog3 xv8 toggle position 3. [25:13] x xv8tog4 xv8 toggle position 4. 10 [12:0] x scp xv9tog1 xv9 toggle position 1. [25:13] x xv9tog2 xv9 toggle position 2. 11 [12:0] x scp xv9tog3 xv9 toggle position 3. [25:13] x xv9tog4 xv9 toggle position 4. 12 [12:0] x scp xv10tog1 xv10 toggle position 1. [25:13] x xv10tog2 xv10 toggle position 2. 13 [12:0] x scp xv10tog3 xv10 toggle position 3. [25:13] x xv10tog4 xv10 toggle position 4. 14 [12:0] x scp xv11tog1 xv11 toggle position 1. [25:13] x xv11tog2 xv11 toggle position 2. 15 [12:0] x scp xv11tog3 xv11 toggle position 3. [25:13] x xv11tog4 xv11 toggle position 4. 16 [12:0] x scp xv12tog1 xv12 toggle position 1. [25:13] x xv12tog2 xv12 toggle position 2. 17 [12:0] x scp xv12tog3 xv12 toggle position 3. [25:13] x xv12tog4 xv12 toggle position 4. 18 [12:0] x scp xv13tog1 xv13 toggle position 1. [25:13] x xv13tog2 xv13 toggle position 2.
ad9927 rev. 0 | page 94 of 100 address data bits default value update type name description 19 [12:0] x scp xv13tog3 xv13 toggle position 3. [25:13] x xv13tog4 xv13 toggle position 4. 1a [12:0] x scp xv14tog1 xv14 toggle position 1. [25:13] x xv14tog2 xv14 toggle position 2 1b [12:0] x scp xv14tog3 xv14 toggle position 3. [25:13] x xv14tog4 xv14 toggle position 4. 1c [12:0] x scp xv15tog1 xv15 toggle position 1. [25:13] x xv15tog2 xv15 toggle position 2. 1d [12:0] x scp xv15tog3 xv15 toggle position 3. [25:13] x xv15tog4 xv15 toggle position 4. 1e [12:0] x scp xv16tog1 xv16 toggle position 1. [25:13] x xv16tog2 xv16 toggle position 2. 1f [12:0] x scp xv16tog3 xv16 toggle position 3. [25:13] x xv16tog4 xv16 toggle position 4. 20 [12:0] x scp xv17tog1 xv17 toggle position 1. [25:13] x xv17tog2 xv17 toggle position 2. 21 [12:0] x scp xv17tog3 xv17 toggle position 3. [25:13] x xv17tog4 xv17 toggle position 4. 22 [12:0] x scp xv18tog1 xv18 toggle position 1. [25:13] x xv18tog2 xv18 toggle position 2. 23 [12:0] x scp xv18tog3 xv18 toggle position 3. [25:13] x xv18tog4 xv18 toggle position 4. 24 [12:0] x scp xv19tog1 xv19 toggle position 1. [25:13] x xv19tog2 xv19 toggle position 2. 25 [12:0] x scp xv19tog3 xv19 toggle position 3. [25:13] x xv19tog4 xv19 toggle position 4. 26 [12:0] x scp xv20tog1 xv20 toggle position 1. [25:13] x xv20tog2 xv20 toggle position 2. 27 [12:0] x scp xv20tog3 xv20 toggle position 3. [25:13] x xv20tog4 xv20 toggle position 4. 28 [12:0] x scp xv21tog1 xv21 toggle position 1. [25:13] x xv21tog2 xv21 toggle position 2. 29 [12:0] x scp xv21tog3 xv21 toggle position 3. [25:13] x xv21tog4 xv21 toggle position 4. 2a [12:0] x scp xv22tog1 xv22 toggle position 1. [25:13] x xv22tog2 xv22 toggle position 2. 2b [12:0] x scp xv22tog3 xv22 toggle position 3. [25:13] x xv22tog4 xv22 toggle position 4. 2c [12:0] x scp xv23tog1 xv23 toggle position 1. [25:13] x xv23tog2 xv23 toggle position 2. 2d [12:0] x scp xv23tog3 xv23 toggle position 3. [25:13] x xv23tog4 xv23 toggle position 4. 2e [12:0] x scp xv24tog1 xv24 toggle position 1. [25:13] x xv24tog2 xv24 toggle position 2. 2f [12:0] x scp xv24tog3 xv24 toggle position 3. [25:13] x xv24tog4 xv24 toggle position 4.
ad9927 rev. 0 | page 95 of 100 table 60. v-sequence (vseq) registers address data bits default value update type name description 00 [0] x scp clpobpol clpob start polarity. [1] x pblkpol pblk start polarity. [5:2] x hold 1 = enable hold function for each vpat group (a, b, c, d). [9:6] x vmask_en 1 = enable freeze/resume for each vpat group (a, b, c, d). [13:10] x concat_grp combine multiple vpat groups together in one sequence. set register equal to 0x01 to enable. [15:14] x vrep_mode defines v-alternation repetition mode. 00 = single pattern alternation for all groups. 01 = two pattern alternation for all groups. 10 = three-pattern alternation for group a. groups b, c, and d follow pattern {0, 1, 1, 0, 1, 1}. 11 = four-pattern alternation for group a. two-pattern alternation for groups b, c, and d. [19:16] x lastreplen_en enable use of last repetition counter for last repetition length of each group. [23:20] x lasttog_en enable the fifth toggle position for all v-signals in each group. [25:24] x hblk_mode selection of hblk modes. 00 = hblk mode 0 (normal six-toggle operation). 01 = hblk mode 1. 10 = hblk mode 2. (address 0x19 to address 0x1e operate differently.) 11 = test only, do not access. 01 [12:0] x scp hdlene hd line length for even lines. [25:13] x hdleno hd line length for odd lines. 02 [23:0] x scp vsgpatsel selects which two toggle positions are used by each v-output when they are configured as vsg pulses (miscellaneous register address 0x1c, fixed register area). 0 = use toggles 1, 2; 1 = use toggles 3, 4. [24] hdlene_13 hd length bit [13] for ev en lines when 14-bit h-counter is enabled. [25] hdleno_13 hd length bit [13] for odd lines when 14-bit h-counter is enabled. 03 [23:0] x scp vpol_a starting polarities for each v-output signal (group a). 04 [23:0] x scp vpol_b starting polarities for each v-output signal (group b). 05 [23:0] x scp vpol_c starting polarities for each v-output signal (group c). 06 [23:0] x scp vpol_d starting polarities for each v-output signal (group d). 07 [23:0] x scp groupsel_0 select which group each xv1 ~ xv12 signal is assigned to. 00 = group a, 01 = group b, 10 = group c, 11 = group d. [1:0]: xv1; [3:2]: xv2 [23:22]: xv12. 08 [23:0] x scp groupsel_1 select which group each xv13 ~ xv24 signal is assigned to. 00 = group a, 01 = group b, 10 = group c, 11 = group d. [1:0]: xv13; [3:2]: xv14 [23:22]: xv24. 09 [4:0] x scp vpatsela selected vpat group for group a, from vpat group 0 ~ 31. [9:5] x vpatselb selected vpat group for group b, from vpat group 0 ~ 31. [14:10] x vpatselc selected vpat group for group c, from vpat group 0 ~ 31. [19:15] x vpatseld selected vpat group for group d, from vpat group 0 ~ 31. 0a [12:0] x scp vstarta start position of selected v-pattern group a. [25:13] x vlena length of selected v-pattern group a. 0b [12:0] x scp vrepa_1 number of repetitions for v-pattern group a for first lines. [25:13] x vrepa_2 number of repetitions for v-pattern group a for second lines. 0c [12:0] x scp vrepa_3 number of repetitions for v-pattern group a for third lines. [25:13] x vrepa_4 number of repetitions for v-pattern group a for fourth lines. 0d [12:0] x scp vstartb start posit ion of selected v-pattern group b. [25:13] x vlenb length of selected v-pattern group b. 0e [12:0] x scp vrepb_odd number of repetitions for v-pattern group b for odd lines. [25:13] x vrepb_even number of repetitions for v-pattern group b for even lines.
ad9927 rev. 0 | page 96 of 100 address data bits default value update type name description 0f [12:0] x scp vstartc start position of selected v-pattern group c. [25:13] x vlenc length of selected v-pattern group c. 10 [12:0] x scp vrepc_odd number of repetitions for v-pattern group c for odd lines. [25:13] x vrepc_even number of repetitions for v-pattern group c for even lines. 11 [12:0] x scp vstartd start position of selected v-pattern group d. [25:13] x vlend length of selected v-pattern group d. 12 [12:0] x scp vrepd_odd number of repetitions for v-pattern group d for odd lines. [25:13] x vrepd_even number of repetitions for v-pattern group d for even lines. 13 [12:0] x scp freeze1 holds the v-outputs at their current levels. [25:13] x resume1 resumes the operation of v-outputs to finish the pattern. 14 [12:0] x scp freeze2 holds the v-outputs at their current levels. [25:13] x resume2 resumes the operation of v-outputs to finish the pattern. 15 [12:0] x scp freeze3 holds the v-outputs at their current levels. [25:13] x resume3 resumes the operation of v-outputs to finish the pattern. 16 [12:0] x scp freeze4 holds the v-outputs at their current levels. [25:13] x resume4 resumes the operation of v-outputs to finish the pattern. 17 [12:0] x scp hblkstart start loca tion for hblk in hblk modes 1 and 2. [25:13] x hblkend end location for hblk in hblk modes 1 and 2. 18 [12:0] x scp hblklen hblk le ngth in hblk modes 1 and 2. [20:13] x hblkrep number of hblk repetitions in hblk modes 1 and 2. [21] x hblkmask_h1 masking polarity for h1/h3/h5/h7 during hblk. [22] x hblkmask_h2 masking polarity for h2/h4/h6/h8 during hblk. [23] x hblkmask_hl masking polarity for hl during hblk. [25:24] x test test use only. set to 0. 19 [12:0] x scp hblktogo1 first hblk toggle position for odd line s, or ra0h1repabc in hblk mode 2 (see hblk mode 2 operation for more information). [25:13] x hblktogo2 second hblk toggle position for odd lines, or ra1h1repabc. 1a [12:0] x scp hblktogo3 third hblk to ggle position for odd lines, or ra2h1repabc. [25:13] x hblktogo4 fourth hblk toggle position for odd lines, or ra3h1repabc. 1b [12:0] x scp hblktogo5 fifth hblk to ggle position for odd lines, or ra4h1repabc. [25:13] x hblktogo6 sixth hblk toggle position for odd lines, or ra5h1repabc. 1c [12:0] x scp hblktoge1 first hblk to ggle position for even lines, or ra0h2repabc. [25:13] x hblktoge2 second hblk toggle position for even lines, or ra1h2repabc. 1d [12:0] x scp hblktoge3 third hblk to ggle position for even lines, or ra2h2repabc. [25:13] x hblktoge4 fourth hblk toggle position for even lines, or ra3h2repabc. 1e [12:0] x scp hblktoge5 fifth hblk to ggle position for even lines, or ra4h2repabc. [25:13] x hblktoge6 sixth hblk toggle pos ition for even lines, or ra5h2repabc. 1f [12:0] x scp hblkstarta hblk repeat area start position a for hblk mode 2. set to 8191 if not used. [25:13] x hblkstartb hblk repeat area start position b for hblk mode 2. set to 8191 if not used. 20 [12:0] x scp hblkstartc hblk repeat area start position c for hblk mode 2. set to 8191 if not used. [13] x vseqalt_en special v- sequence alternation enable. [14] x valt_map 1= enables operation of valtsel0_even/odd, valtsel1_even/odd registers in freeze/resume registers. must be enabled if special valt mode is used. [17:15] x spc_pat_en 1 = enables use of special vertical pattern insertion into vpata sequence. [0]: use vpatb as the special pattern. [1]: use vpatc as the special pattern. [2]: use vpatd as the special pattern.
ad9927 rev. 0 | page 97 of 100 address data bits default value update type name description 21 [2:0] x scp hblkalt_pat1 hblk mode 2, repeat area 0 pattern for odd lines. [6:4] x hblkalt_pat2 hblk mode 2, repeat area 0 pattern for odd lines. [10:8] x hblkalt_pat3 hblk mode 2, repeat area 0 pattern for odd lines. [14:12] x hblkalt_pat4 hblk mode 2, repeat area 0 pattern for odd lines. [18:16] x hblkalt_pat5 hblk mode 2, repeat area 0 pattern for odd lines. [22:20] x hblkalt_pat6 hblk mode 2, repeat area 0 pattern for odd lines. 22 [12:0] x scp clpobtog1 clpob toggle position 1. [25:13] x clpobtog2 clpob toggle position 2. 23 [12:0] x scp pblktog1 pblk toggle position 1. [25:13] x pblktog2 pblk toggle position 2. 24 [12:0] x scp lastreplen_a last repetiti on length for group a. set equal to vlena. [25:13] x lastreplen_b last repetition length for group b. set equal to vlenb. 25 [12:0] x scp lastreplen_c last repetiti on length for group c. set equal to vlenc. [25:13] x lastreplen_d last repetition length for group d. set equal to vlend. 26 [12:0] x scp lasttog_a optional fifth toggle position for group a. [25:13] x lasttog_b optional fifth toggle position for group b. 27 [12:0] x scp lasttog_c optional fifth toggle position for group c. [25:13] x lasttog_d optional fifth toggle position for group d.
ad9927 rev. 0 | page 98 of 100 table 61. field registers address data bits default value update type name description 00 [4:0] x vd seq0 selected v-sequence for first region in the field. [9:5] x seq1 selected v-sequence for second region in the field. [14:10] x seq2 selected v-sequence for third region in the field. [19:15] x seq3 selected v-sequence for fourth region in the field. [24:20] x seq4 selected v-sequence for fifth region in the field. 01 [4:0] x vd seq5 selected v-sequence for sixth region in the field. [9:5] x seq6 selected v-sequence for seventh region in the field. [14:10] x seq7 selected v-sequence for eighth region in the field. [19:15] x seq8 selected v-sequence for ninth region in the field. [21:20] mult_sweep0 enables multiplier mode and/or sweep mode for region 0. 0: multiplier off/sweep off; 1: multiplier off/sweep on; 2: multiplier on/sweep off; 3: multiplier on/sweep on. [23:22] mult_sweep1 enab les multiplier mode and/or sweep mode for region 2. [25:24] mult_sweep2 enab les multiplier mode and/or sweep mode for region 1. 02 [12:0] x vd hdlastlen hd last line leng th. line length of last line in the field. [14:13] x mult_sweep3 enables multiplier mode and/or sweep mode for region 3. [16:15] x mult_sweep4 enables multiplier mode and/or sweep mode for region 4. [18:17] x mult_sweep5 enables multiplier mode and/or sweep mode for region 5. [20:19] x mult_sweep6 enables multiplier mode and/or sweep mode for region 6. [22:21] x mult_sweep7 enables multiplier mode and/or sweep mode for region 7. [24:23] x mult_sweep8 enables multiplier mode and/or sweep mode for region 8. [25] hdlastlen_13 hd last line length bit [13] when 14-bit h-counter is enabled. 03 [12:0] x vd scp0 v-sequence change position 0. [25:13] x scp1 v-sequence change position 1. 04 [12:0] x vd scp2 v-sequence change position 2. [25:13] x scp3 v-sequence change position 3. 05 [12:0] x vd scp4 v-sequence change position 4. [25:13] x scp5 v-sequence change position 5. 06 [12:0] x vd scp6 v-sequence change position 6. [25:13] x scp7 v-sequence change position 7. 07 [12:0] x vd scp8 v-sequence change position 8. [25:13] vdlen vd field length (number of lines in the field). 08 [12:0] x vd sgactline1 sg active line 1. [25:13] x sgactline2 sg active line 2 (set to sg active line 1 or maximum if not used). 09 [23:0] x vd sgmask masking of vsg outputs during sg active line. 0a [12:0] x vd clpmaskstart1 clpob mask region 1 start position. set to 8191 to disable. [25:13] x clpmaskend1 clpob mask region 1 end position. set to 0 to disable. 0b [12:0] x vd clpmaskstart2 clpob mask re gion 2 start position. set to 8191 to disable. [25:13] x clpmaskend2 clpob mask region 2 end position. set to 0 to disable. 0c [12:0] x vd clpmaskstart3 clpob mask region 3 start position. set to 8191 to disable. [25:13] x clpmaskend3 clpob mask region 3 end position. set to 0 to disable. 0d [12:0] x vd pblkmaskstart1 pblk mask re gion 1 start position. set to 8191 to disable. [25:13] x pblkmaskend1 pblk mask regi on 1 end position. set to 0 to disable. 0e [12:0] x vd pblkmaskstart2 pblk mask re gion 2 start position. set to 8191 to disable. [25:13] x pblkmaskend2 pblk mask regi on 2 end position. set to 0 to disable. 0f [12:0] x vd pblkmaskstart3 pblk mask re gion 3 start position. set to 8191 to disable. [25:13] x pblkmaskend3 pblk mask regi on 3 end position. set to 0 to disable.
ad9927 rev. 0 | page 99 of 100 outline dimensions b c d e f g h j k a seating plane 0.15 min detaila 0.45 0.40 0.35 ball diameter coplanarity 0.10 0.65 bsc 7.15 bsc sq 10 98 765 4 3 21 a1 corner index area top view ball a1 pad corner detail a * 1.40 max 0.65 min 11 12 l m 9.10 9.00 sq 8.90 * compliant to jedec standards mo-225 with the exception of package height. figure 102. 128-lead chip scale package ball grid array [csp_bga] 9 mm 9 mm body (bc-128) dimensions shown in millimeters ordering guide model temperature range package description package option AD9927BBCZ 1 C25c to +85c 128-lead csp_bga bc-128 AD9927BBCZrl 1 C25c to +85c 128-lead csp_bga bc-128 1 z = pb-free part.
ad9927 rev. 0 | page 100 of 100 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05892-0-1/06(0)

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